Memory System Using Shared Channel and Clock Edge Segmentation
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Solution Overview
Problem
Current Dynamic Random Access Memory (DRAM) technologies face challenges in meeting high performance requirements across various applications due to the need for multiple communication channels, which increases area, cost, and power consumption.
Innovation Solution
A memory system where multiple storage chips share a common communication channel, utilizing different clock edges of a first clock signal with a first clock cycle, and distinguishing these edges using a second clock signal with a greater cycle, allowing each storage chip to perform information interaction with a control chip without increasing information interaction quality, thereby reducing the number of communication channels, cost, and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple communication channels are used for each storage chip, then information interaction quality is improved, but area, cost, and power consumption increase
Solution Approach 1:
Multiple storage chips share a single common communication channel with the control chip, consolidating what would traditionally be separate dedicated channels into one shared resource. This merging approach maintains information interaction quality through protocol-based differentiation while reducing the overall number of physical channels required.
Solution Approach 2:
The shared communication channel is segmented in time through different clock edges (rising and falling edges) and clock cycles. Different storage chips are assigned to communicate at different time segments defined by the clock signal edges, allowing multiple chips to share the same physical channel without simultaneous conflicts.
2Reliability
If multiple communication channels are used for each storage chip, then information interaction quality is improved, but manufacturing cost increases
Solution Approach 1:
By merging multiple dedicated communication channels into one shared channel, the patent reduces the number of physical connections, routing structures, and signal integrity requirements that need to be manufactured and tested, thereby lowering manufacturing costs while maintaining functional equivalence.
3Reliability
If multiple communication channels are used for each storage chip, then information interaction quality is improved, but power consumption increases
Solution Approach 1:
The patent merges multiple communication channels into one shared channel, reducing the total number of active signal paths. Fewer channels mean fewer simultaneous signal transitions and less cumulative power consumption across the memory system while preserving information interaction quality through time-division.
4Quantity of substance
If different clock edges are used for information interaction, then storage density is improved, but device complexity increases
Solution Approach 1:
The patent employs dynamic clock signal characteristics (different edges and cycles) to encode different communication modes. The clock signal dynamically switches between different edges (rising/falling) and cycles to differentiate between various storage chip operations, enabling high storage density without requiring complex dedicated channels for each chip.
Data Source
AI summary
A memory is provided. The memory includes: a control chip; and a plurality of storage chips, in which the plurality of storage chips are electrically connected with the control chip via a common communication channel, the plurality of storage chips are configured to perform information interaction with the control chip by adopting different clock edges of a first clock signal, the first clock signal has a first clock cycle, the different clock edges include two consecutive rising edges and/or two consecutive falling edges, the plurality of storage chips are further configured to receive a second clock signal and distinguish the different clock edges based on the second clock signal, and a second clock cycle of the second clock signal is greater than the first clock cycle.