Memory Device Shared Pin Interface for Command Address Signals
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Solution Overview
Problem
Modern memory devices require a large number of input pins to support various command and address combinations, leading to increased size and cost.
Innovation Solution
Implementing a shared interface with dedicated and shared pins on both the command and address buses, allowing for flexible allocation of pins between command and address inputs in each cycle, reducing the overall pin count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dedicated pins are used for each command and address input, then the memory device can support all command and address combinations reliably, but the number of pins increases leading to larger device size and higher cost
Solution Approach 1:
The patent applies multi-functionality by designing pins that can serve dual purposes: dedicated pins handle their specific signal types (command or address), while shared pins dynamically switch between command and address functions based on timing signals. This allows the same physical pin to perform multiple roles, reducing the total pin count while maintaining full support for all command and address combinations.
Solution Approach 2:
The patent implements dynamic pin allocation where shared pins change their function over time based on clock cycles and timing signals. During certain cycles, shared pins receive command inputs; during other cycles, they receive address inputs. This temporal multiplexing allows the system to adapt pin usage dynamically, resolving the contradiction between needing many pins for reliability and minimizing pins for cost reduction.
2Quantity of substance
If the number of pins is reduced using shared interfaces, then device size and cost decrease, but the complexity of managing shared pins between command and address functions increases
Solution Approach 1:
The patent applies preliminary action by pre-establishing dedicated pins for command and address inputs before the shared pins are allocated. This hierarchical allocation simplifies management: dedicated pins handle their signals continuously without conflict, while shared pins are only involved when needed, with their function predetermined by the timing signal state. This preliminary structuring reduces the complexity burden compared to fully dynamic sharing.
3Quantity of substance
If shared pins are used for both command and address inputs, then the pin count is reduced, but the timing and coordination of signal reception becomes more challenging
Solution Approach 1:
The patent applies periodic action by using clock cycles to rhythmically alternate the function of shared pins between command and address reception. The timing signals operate periodically, enabling shared pins to receive command inputs during certain clock cycles and address inputs during other cycles. This periodic switching provides a predictable, regular pattern that simplifies timing coordination compared to arbitrary or aperiodic signal assignment.
Data Source
AI summary
Apparatus and methods for communicating command and address inputs to a memory device. In one embodiment, a memory device includes a shared bus interface defined by a portion of pins from a command bus interface and a portion of pins from an address bus interface. Each portion of pins is configured to receive address and command inputs, depending a given command/address combination being asserted by a memory controller.