Memory Sharing System With Delay PLL Clock Alignment
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Solution Overview
Problem
Current memory systems face challenges in meeting the increasing demand for higher data transmission rates, particularly in real-time applications, as existing memory devices like DDR-DRAM may become insufficient due to limitations in clock frequency and power consumption.
Innovation Solution
A memory sharing system comprising a master control device, a slave control device with a delay phase-locked loop (DLL), and a memory device, where the master control device transmits a clock signal, and the slave control device tracks it to generate aligned output signals, allowing for efficient access and reducing power consumption by activating the memory clock signal only during data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency of memory devices is increased to meet higher data transmission rates, then the data transmission rate is improved, but the power consumption increases
Solution Approach 1:
The patent implements periodic action by enabling the memory clock signal only during data access operations and disabling it during idle periods. The master control device controls the timing of clock signal activation, and the slave control device uses a delay-locked loop (DLL) to generate synchronized clock edges, ensuring the memory operates periodically only when needed, thus reducing power consumption while maintaining high data transmission rates during active operations
Solution Approach 2:
The patent applies dynamics by making the clock signal conditional and adaptive rather than continuous. The slave control device dynamically generates clock edges based on received data patterns, and the system adapts the clock timing through the DLL mechanism to match actual data access requirements, allowing the memory system to operate at high speeds when needed while consuming minimal power during idle states
2Productivity
If multiple control devices access the memory device simultaneously, then the access efficiency is improved, but page conflicts increase
Solution Approach 1:
The patent introduces an intermediary arbitration mechanism where the master control device acts as a coordinator for memory access requests. The slave control device sends access requests to the master, which arbitrates and grants access rights selectively. This intermediary arbitration system enables multiple control devices to access the memory efficiently while preventing page conflicts through controlled access timing and synchronization
3Speed
If the clock signal is continuously activated to maintain high data transmission rates, then the speed is improved, but the power consumption increases
Solution Approach 1:
The patent implements periodic action by enabling the memory clock signal only during data access operations and disabling it during idle periods. The master control device controls the timing of clock signal activation, and the slave control device uses a delay-locked loop (DLL) to generate synchronized clock edges, ensuring the memory operates periodically only when needed, thus reducing power consumption while maintaining high data transmission rates during active operations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The system effectively supports high data transmission rates, reduces power consumption, and minimizes page conflicts by aligning clock signals and enabling efficient access to memory devices, making it suitable for next-generation memory devices.
Implementation Method 1
The slave control device, coupled to the memory device via the data bus and coupled to the master control device, comprises a delay phase-locked loop (hereinafter 'delay PLL' or 'DLL'). The slave control device receives the clock signal, and the delay PLL tracks the clock signal.
Data Source
AI summary
A memory sharing system includes a master control device, a slave control device and a memory device. The master control device selectively generates a clock signal to the memory device. The slave control device receives and tracks the clock signal via a delay phase locked loop (DLL) to generate and align an output signal with the clock signal. The master control device arbitrates an access right.