Memory Sharing Device for Distributed Data Access
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Solution Overview
Problem
In distributed systems, the existing switched network-based information sharing method leads to excessive CPU consumption and reduced reliability due to the need for both CPUs in the acquirer and provider systems to participate in data transfer, causing performance waste and potential data unavailability if the provider CPU is faulty.
Innovation Solution
A data access system with a memory sharing resource pool, where memory sharing devices with unified addressing store data and handle memory access requests independently, reducing the workload on provider CPUs and ensuring data availability by distributing data storage across multiple devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the switched network-based information sharing method is used, then data can be shared between distributed systems, but the CPU performance in the provider system is excessively consumed
Solution Approach 1:
The patent extracts the data transfer function from the CPU and implements it in the DMA controller. The CPU only needs to initiate the transfer by writing the source address, destination address, and transfer length to the DMA controller, then the DMA controller independently completes the entire data transfer process without further CPU intervention, thus freeing up CPU resources for computation tasks.
Solution Approach 2:
The patent introduces the DMA controller as an intermediary between the memory and I/O devices. This intermediary handles all data transfer operations, including address generation, memory access, and data routing, allowing the CPU to focus on processing while the DMA controller manages communication between components.
2Productivity
If both CPUs participate in data transfer processing, then data can be transferred between systems, but the system reliability is reduced due to potential CPU faults
Solution Approach 1:
The patent removes the data transfer execution function from the CPU and assigns it to the DMA controller. The CPU only performs high-level operations of setting transfer parameters, while the DMA controller handles the actual data movement independently, reducing the risk of CPU faults affecting data transfer operations.
Solution Approach 2:
The DMA controller is designed to autonomously manage the entire data transfer process without requiring continuous CPU supervision. It independently generates addresses, accesses memory, controls data flow, and manages transfer timing, making the system more reliable by reducing dependency on CPU availability during transfer operations.
3Reliability
If the CPU handles all data transfer operations, then accurate data transfer can be ensured, but the response speed is reduced due to CPU processing overhead
Solution Approach 1:
The DMA controller serves as a specialized intermediary optimized for high-speed data transfer operations. It uses dedicated hardware circuits for address generation, incrementing, and memory access control, which operate much faster than general-purpose CPU instructions, thereby significantly increasing data transfer speed while maintaining accuracy through hardware-level error checking.
Solution Approach 2:
The patent replaces the software-based data transfer control mechanism (CPU executing transfer instructions) with a hardware-based DMA control mechanism. This substitution eliminates the overhead of instruction fetching, decoding, and execution, allowing data transfers to proceed at near-memory-speed rates without CPU intervention.
Data Source
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AI summary
The present invention relates to a data access system, including: a memory sharing resource pool formed by at least two memory sharing devices, and at least two control devices corresponding to the memory sharing devices, where any memory sharing device in the at least two memory sharing devices includes unifiedly addressed memory units that are configured to store data, and any memory sharing device acquires, under control of one control device corresponding to the memory sharing device in the at least two control devices, data in a memory unit in any memory sharing device in the memory sharing resource pool; any control device in the at least two control devices is connected to the at least two memory sharing devices by using a communication interface and acquires, according to address information that has undergone the unified addressing, data in a memory unit in any of at least one memory sharing device in the memory sharing resource pool by using a memory sharing device that is corresponding to the any control device and is in the memory sharing resource pool.