Hardware Subsystem Memory Sharing for Packet Transfer
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Solution Overview
Problem
In resource-constrained operating environments, existing direct memory access (DMA) methods are inefficient due to expensive buffer memory usage and high power consumption, especially in packet-based communication devices, where buffering is required at multiple stages and memory reuse is limited, especially in ultra-low power applications like short-range wireless communications.
Innovation Solution
Implementing a system where components share memory by allocating a portion to one component, allowing it to access and send information to another, thereby avoiding DMA copying and enabling real-time memory resource adjustment based on packet size and wireless channels, while reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DMA is used for data transfer between CPU and hardware subsystem, then data transfer efficiency is improved, but memory cost and power consumption increase
Solution Approach 1:
The patent merges the buffer memory functionality into the hardware subsystem's existing memory resources rather than allocating separate DMA buffer memory. The network processor directly accesses packet data in hardware subsystem memory, eliminating the need for dedicated DMA buffers and reducing overall memory usage while maintaining transfer efficiency.
Solution Approach 2:
The hardware subsystem memory serves multiple functions: it stores packet data for processing, acts as the transfer buffer for network operations, and can be reused for other hardware operations. This multi-functional use eliminates the need for specialized DMA buffer memory, reducing both memory cost and power consumption.
2Reliability
If buffer memory is allocated in hardware subsystem for packet buffering, then QoS requirements are met, but memory reuse is prevented and system capability is reduced
Solution Approach 1:
The patent implements dynamic memory allocation where the hardware subsystem can allocate memory resources to different functions based on real-time needs. When packet buffering is required, memory is allocated for QoS; when not needed, the same memory can be reused for other operations, providing adaptability while maintaining service quality.
Solution Approach 2:
The system recovers and reuses buffer memory after packet processing is complete. The hardware subsystem releases memory resources back to the general pool after packets are processed, allowing the same memory to be reused for subsequent operations rather than being permanently allocated.
3Reliability
If extensive buffering is implemented at multiple hardware stages, then packet processing reliability is improved, but memory resource consumption increases
Solution Approach 1:
The patent combines buffering operations across multiple hardware stages into a unified memory management approach. Instead of each stage having separate buffers, the system uses shared hardware subsystem memory with coordinated access, reducing total memory requirements while maintaining processing reliability through coordinated data flow management.
Data Source
AI summary
An apparatus includes first and second components, a memory, and an allocator configured to allocate a portion of the memory to the first component, wherein the first component is configured to access the allocated portion of the memory and to send information to the second component to provide the second component with access to the allocated portion of the memory.