Memory Input Testing With Shift-Cycle Capture for SAF Detection
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Solution Overview
Problem
Existing memory device testing methods fail to effectively detect stuck-at-fault (SAF) defects at input pins due to extended read and write intervals that conceal the defects, and require interposing connections to mask inputs, which introduce complexity and signal loss.
Innovation Solution
A test interface is introduced to selectively adjust clock signals, allowing the memory device to capture inputs from a previous or current shift cycle without additional interposed connections, thereby enabling SAF defect detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If extended read and write intervals are used in memory devices, then memory operation flexibility is improved, but stuck-at-fault defects at input pins become undetectable
Solution Approach 1:
The patent applies preliminary action by capturing inputs at two different time points (current and previous shift cycles) before the extended read/write intervals can conceal defects. The test interface proactively latches inputs from both the current shift cycle and the previous shift cycle, ensuring that if a stuck-at-fault defect exists, it will be detected in at least one of the captured values before the memory operations mask the defect.
2Reliability
If interposed connections are added to mask inputs for defect detection, then defect detection capability is improved, but device complexity increases
Solution Approach 1:
The test interface circuit performs multiple functions: it generates clock signals for the memory device, it captures inputs from both current and previous shift cycles, and it enables defect detection. By integrating these functions into a single multi-functional test interface rather than adding separate interposed connections and masking circuits, the patent achieves defect detection capability while minimizing the increase in device complexity.
3Reliability
If interposed connections are added to mask inputs, then defect detection capability is improved, but signal loss occurs
Solution Approach 1:
Instead of using interposed connections that physically intercept and potentially lose signals, the patent creates a logical copy of the input signals by capturing them at two different time points through the test interface. The clock signals and input data are replicated in the latches of the test interface, allowing defect detection through comparison without introducing physical signal paths that would cause signal loss.
Data Source
AI summary
This document describes systems and techniques for detecting stuck-at-fault (SAF) defects at input pins of a memory device. For example, a system includes a memory device to receive data and address inputs. A clock interface is configured to generate a memory clock signal according to a first clock signal received at a clock input. A logic interface is configured to provide the inputs to the memory device during a shift cycle according to a second clock signal received at a logic clock input. A test interface is configured to receive a system clock signal and to selectively adjust the first clock signal and the second clock signal to cause address signals presented to the address inputs and data signals presented to the data inputs to cause the memory device to capture the inputs from a previous shift cycle or a current shift cycle to enable identification of stuck-at-fault defects.