Memory Array Shunt Rows for Faster Low-Power MTJ-OTP Writing
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Solution Overview
Problem
The scaling down of semiconductor integrated circuits (ICs) leads to increased power consumption and limited write current due to excessive charging of source-line (SL) resistance, which hinders performance and reliability of memory cells, particularly in Magnetic Tunnel Junction-One-Time Programmable (MTJ-OTP) devices.
Innovation Solution
Incorporating a memory array with additional rows containing shunt components, each comprising a shunt transistor and resistor, and controlling these components through a shunt enable signal to reduce write-path resistance and increase write current while maintaining read-path resistance, thereby improving performance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If source-line resistance is reduced to increase write current, then write speed improves, but power consumption increases due to excessive charging of SL resistance
Solution Approach 1:
The patent applies preliminary action by pre-charging the source line to the write voltage level before the actual write operation. This is achieved by activating the shunt transistor to connect the source line to the voltage source, preparing the SL in advance so that when the write operation occurs, the line is already charged and ready to deliver current without requiring excessive charging during the operation itself.
Solution Approach 2:
The shunt transistor serves as an intermediary component between the voltage source and the source line. It controls the charging process by selectively connecting or disconnecting the SL from the voltage source, enabling precise control over when charging occurs. This intermediary mechanism allows the system to charge the SL only when needed, avoiding continuous power consumption while maintaining the ability to quickly deliver write current.
2Productivity
If more devices are integrated into a single chip through scaling down, then production efficiency increases, but write current is limited due to excessive charging of source-line resistance
Solution Approach 1:
The shunt transistor enables preliminary charging of the source line to the required voltage level before write operations begin. This pre-charging mechanism ensures that even as more devices are integrated and SL resistance increases, the line is already prepared with sufficient voltage to drive the required write current through the increased resistance without limiting the overall power available for writing.
Solution Approach 2:
The patent introduces dynamic control of the source line through the shunt transistor, which can selectively enable or disable the connection between the voltage source and the SL based on operational needs. This dynamic adjustment allows the system to adapt to varying write current requirements across multiple integrated devices, optimizing power delivery while maintaining the ability to scale device integration without being constrained by fixed SL resistance limitations.
Data Source
AI summary
A memory device includes a memory array including a plurality of first memory cells physically arranged over a plurality of rows and a plurality of first columns. Each of the plurality of first memory cells includes a memory transistor serially coupled to a memory resistor. The memory device includes one additional row arranged next to the memory array. The additional row includes a plurality of first shunt components, and each of the plurality of first shunt components includes a shunt transistor and a shunt resistor. Respective first source/drain terminals of the shunt transistors of the first shunt components are electrically coupled to one another, and respective second source/drain terminals of the shunt transistors of the first shunt components are electrically coupled to one another and further electrically coupled to respective first source/drain terminals of the memory transistors of the first memory cells.