Memory-Side Cache Compression via Block Replacement
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Solution Overview
Problem
Conventional memory architectures face suboptimal performance and increased power consumption due to frequent cache misses in memory-side caches, which lead to data retrieval from slower far memory, and decompressing these caches increases latency and overhead.
Innovation Solution
A compression scheme that pairs processor-side cache lines with memory-side cache blocks or sub-blocks using techniques like frequent pattern compression, base-delta-immediate, run length encoding, and Huffman encoding to create compressed blocks that satisfy size conditions, allowing for efficient replacement and reduction of cache misses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If each block of the memory-side cache is compressed to make room for more data, then cache capacity is improved, but decompression latency and overhead increase
Solution Approach 1:
The patent pre-computes and stores compression metadata (such as base values, delta values, and compression patterns) in the cache block header or adjacent storage during the cache fill operation, before any decompression is needed. This preliminary preparation allows the decompression process to simply apply pre-calculated values rather than performing complex compression algorithms during cache access, thereby reducing decompression latency while maintaining high cache capacity through compression
2Quantity of substance
If decompression is performed on a block-by-block basis, then cache capacity is improved, but overhead increases particularly for critical path operations
Solution Approach 1:
The patent divides the cache block into multiple sub-blocks or cache lines, each with its own compression metadata and decompression characteristics. This segmentation allows the decompression process to operate on smaller, more manageable units with lower overhead, and enables selective decompression of only those sub-blocks that are actually needed, rather than decompressing entire blocks unnecessarily
Solution Approach 2:
The patent implements self-service decompression where the compression metadata stored with each cache block contains all necessary information for automatic decompression without requiring external control logic. The decompression unit simply reads the metadata and applies the appropriate decompression algorithm autonomously, reducing control overhead and simplifying the decompression process
3Reliability
If frequent misses occur in the memory-side cache, then data must be retrieved from far memory, but this increases power consumption and reduces performance
Solution Approach 1:
The patent changes the data representation parameter in the memory-side cache from uncompressed to compressed format, allowing more data to be stored in the same physical space. This parameter change increases the effective cache capacity and improves the cache hit rate, thereby reducing the frequency of misses that would require expensive and power-consuming retrievals from far memory
Data Source
AI summary
Systems, apparatuses and methods may provide for identifying a first block and a second block, wherein the first block includes a first plurality of cache lines, the second block includes a second plurality of cache lines, and the second block resides in a memory-side cache. Additionally, each cache line in the first plurality of cache lines may be compressed with a corresponding cache line in the second plurality of cache lines to obtain a compressed block that includes a third plurality of cache lines. In one example, the second block is replaced in the memory-side cache with the compressed block if the compressed block satisfies a size condition.