3D Memory Cell Layout With Sidewall Oxide for Low Parasitic Coupling
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Solution Overview
Problem
Current semiconductor devices, particularly memory devices, face challenges in achieving high reliability, integration density, operating speed, and reduced power consumption, especially with the limitations of existing oxide semiconductor technologies.
Innovation Solution
The development of a memory device design that includes a plurality of memory elements with transistors and capacitors, where the gate electrode of each transistor is electrically connected to a wiring structure, and an oxide layer is positioned along the side surface of the wiring, with a specific distance configuration to optimize performance and integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the distance between adjacent memory element groups is increased to reduce parasitic capacitance and improve reliability, then the integration density and operating speed deteriorate due to larger device area
Solution Approach 1:
The patent introduces oxide layers extending vertically along the side surfaces of word lines, transforming a two-dimensional planar separation problem into a three-dimensional solution. This vertical dimension allows adjacent memory element groups to be positioned closer in the planar view while maintaining electrical isolation through the oxide layer barrier, thereby resolving the contradiction between reducing parasitic capacitance and maintaining high integration density
Solution Approach 2:
The oxide layer acts as an intermediary substance between adjacent memory element groups, providing electrical isolation and reducing parasitic capacitance without requiring increased physical separation. This mediator enables closer positioning of memory elements while maintaining reliability, directly addressing the contradiction between integration density and data retention accuracy
2Reliability
If oxide layers are added along the side surfaces of word lines to reduce parasitic capacitance, then manufacturing complexity increases
Solution Approach 1:
The oxide layer formation process is merged with the existing gate insulating layer deposition process. The same oxide semiconductor material and deposition conditions are used for both the gate insulating layer and the side-surface oxide layers, reducing manufacturing complexity while achieving parasitic capacitance reduction
Solution Approach 2:
The oxide layer serves multiple functions simultaneously: it acts as a gate insulating layer for transistor operation, provides electrical isolation between adjacent memory element groups, and reduces parasitic capacitance. This multi-functionality eliminates the need for separate structures, simplifying the overall device architecture despite the added vertical dimension
Data Source
AI summary
A novel memory device is provided. The memory device includes a plurality of first wirings extending in a first direction, a plurality of memory element groups, and an oxide layer extending along a side surface of the first wiring. Each of the memory element groups includes a plurality of memory elements. Each of the memory elements includes a first transistor and a capacitor. A gate electrode of the first transistor is electrically connected to the first wiring. The oxide layer includes a region in contact with a semiconductor layer of the first transistor. A second transistor is provided between the adjacent memory element groups. A high power supply potential is supplied to one or both of a source electrode and a drain electrode of the second transistor.