Memory Device Sidewall Spacer Formation
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Solution Overview
Problem
The existing methods for manufacturing sidewall spacers in memory devices are limited by the constraint that the thickness of spacers in the memory array determines the thickness of spacers in peripheral circuits, which can hinder precise formation and depth of source/drain regions in peripheral circuits due to densely packed word lines in the memory array.
Innovation Solution
A method is developed to form sidewall spacers with different thicknesses using a single layer of spacer material, where a first sidewall spacer with a specific thickness is formed adjacent to word lines in the memory array, and a second sidewall spacer with a greater thickness is formed adjacent to transistor structures in peripheral circuits, utilizing anisotropic etching and epitaxial silicon to achieve this differentiation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single thickness of sidewall spacer is formed for both memory array and peripheral circuits, then the manufacturing process is simplified, but the source/drain regions in peripheral circuits cannot be formed with precise depth and location
Solution Approach 1:
The patent divides the spacer formation process into two independent stages: first forming spacers in the memory array with a controlled etch process, then forming spacers in peripheral circuits with a separate deposition process. This segmentation allows each region to have optimized spacer thickness independent of the other, resolving the contradiction between process simplicity and manufacturing precision.
Solution Approach 2:
The patent applies different spacer formation methods to different regions: the memory array receives spacers formed by anisotropic etching with controlled thickness, while peripheral circuits receive spacers formed by additional deposition to achieve greater thickness. This local differentiation enables precise control of source/drain regions in peripheral circuits without affecting memory array performance.
2Manufacturing precision
If thicker spacers are formed in peripheral circuits to enable deeper source/drain regions, then source/drain formation precision is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent performs preliminary formation of memory array spacers through anisotropic etching before forming peripheral circuit spacers. This preliminary action establishes a foundation that allows subsequent deposition of additional spacer material in peripheral circuits without interfering with memory array structures, thereby enabling thicker spacers where needed while maintaining overall process manageability.
Solution Approach 2:
The patent uses a masking layer as an intermediary element that selectively protects memory array regions during the peripheral circuit spacer formation process. This intermediary allows the deposition of thicker spacer material in peripheral circuits while preventing material deposition in memory array regions, thus managing process complexity through selective masking.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the precise formation of deeper and more accurately located source/drain regions in peripheral circuits by enabling thicker spacers in peripheral circuits compared to the memory array, enhancing the overall performance and capabilities of memory devices.
Implementation Method 1
performing an anisotropic etching process on the layer of spacer material to define a first sidewall spacer for the word line structure
Implementation Method 2
forming a layer of epitaxial silicon on exposed portions of a semiconducting substrate between first sidewall spacers positioned on adjacent word line structures
Data Source
Figure 1A
Figure 1B
Figure 2A
AI summary
The present invention is generally directed to a method of manufacturing sidewall spacers on a memory device, and a memory device comprising such sidewall spacers. In one illustrative embodiment, the method includes forming sidewall spacers on a memory device comprised of a memory array and at least one peripheral circuit by forming a first sidewall spacer adjacent a word line structure in the memory array, the first sidewall spacer having a first thickness and forming a second sidewall spacer adjacent a transistor structure in the peripheral circuit, the second sidewall spacer having a second thickness that is greater than the first thickness, wherein the first and second sidewall spacers comprise material from a single layer of spacer material. In one illustrative embodiment, the device includes a memory array comprised of a plurality of word line structures, each of the plurality of word line structures having a first sidewall spacer formed adjacent thereto, the first sidewall spacer having a first thickness, and a peripheral circuit comprised of at least one transistor having a second sidewall spacer formed adjacent thereto, the second sidewall spacer having a second thickness that is greater than the first thickness, the first and second sidewall spacers comprised of a material from a single layer of spacer material.