Memory Signal Verification via Multi-Bit Check Path Comparison
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current signal verification mechanisms in the memory field, such as parity checks, suffer from low accuracy rates, leading to potential system disorders due to signal discrepancies between the memory and the memory controller.
Innovation Solution
A signal verification system that includes a memory controller, a memory, and two transmission paths, with conversion components and a comparison module, where the memory controller sends to-be-check signals through a multi-port channel and a check signal through a single-port channel, allowing for conversion and comparison to detect signal errors, thereby improving accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If parity check is used for signal verification, then the verification mechanism is simple to implement, but the accuracy rate is low
Solution Approach 1:
The patent transforms single-bit signal verification into multi-bit signal verification by introducing conversion components that encode multiple data bits into a single verification signal. This dimensional transformation allows the system to detect multiple error patterns simultaneously, significantly improving verification accuracy while maintaining manageable system complexity through structured encoding schemes.
Solution Approach 2:
The patent changes the fundamental parameter of signal representation from single-bit to multi-bit format. By converting verification signals into multi-bit sequences with specific encoding patterns, the system gains the ability to detect and distinguish between different types of signal errors, thereby improving accuracy without requiring overly complex verification mechanisms.
2Reliability
If single-bit signals are transmitted, then the transmission path is simple, but the error detection capability is limited
Solution Approach 1:
The patent segments the verification process into multiple independent transmission paths, each carrying multi-bit signals. By dividing the verification task across multiple parallel paths with distinct encoding schemes, the system achieves enhanced error detection capability while keeping each individual transmission path relatively simple and manageable.
Solution Approach 2:
The patent introduces conversion components as intermediary elements between the data transmission path and the verification path. These intermediaries transform single-bit signals into multi-bit verification signals, enabling more sophisticated error detection without directly complicating the core transmission paths. The conversion components act as mediators that add verification capability while maintaining transmission simplicity.
Data Source
AI summary
Embodiments of the present disclosure provide a signal verification system, including: a memory controller, a memory, and a first transmission path and a second transmission path connected between the memory controller and the memory, where the memory controller sends one or more to-be-check signals through the first transmission path, and sends a check signal through the second transmission path, where the second transmission path is a single-port channel, and the check signal is a multi-bit signal; and a comparison module, connected to an output end of a first conversion component and an output end of the second transmission path, and configured to obtain and compare an output signal of the first conversion component and an output signal of the second transmission path.