Adjustable Signal Path Delay for Memory Command Timing Alignment
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Solution Overview
Problem
In semiconductor memory, the high frequency of memory clock signals and multi-data rate operations complicate the timing of internal command and clock signals, leading to potential misalignment and incorrect data transfer due to varying propagation delays caused by power, voltage, and temperature conditions, resulting in improper memory operation.
Innovation Solution
The implementation of a signal path with an adjustable delay circuit and a forward path measurement circuit to synchronize command and clock signals, using a delay-locked loop clock circuit to provide a delayed clock signal and adjust the propagation delay to satisfy latency requirements, ensuring correct timing of command signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the propagation delay of clock and command paths is modeled to be the same, then the timing of internal command and clock signals can be synchronized, but delays and counter circuitry must run continuously causing higher power consumption
Solution Approach 1:
The patent implements a calibration mode that operates periodically rather than continuously. A calibration command is executed at specific intervals to measure and adjust propagation delays, while the delay circuits operate in a held state between calibrations. This periodic calibration approach maintains timing synchronization reliability while dramatically reducing power consumption compared to continuous operation.
Solution Approach 2:
The patent performs delay calibration in advance during a dedicated calibration mode before normal operation begins. The measured propagation delays are stored and used to pre-adjust the delay circuits, eliminating the need for continuous real-time adjustment during data operations. This preliminary calibration ensures timing synchronization is established before the system enters its low-power operational state.
2Reliability
If delay circuitry is added to compensate for long propagation delay, then timing of internal signals can be corrected, but variations due to power, voltage, and temperature conditions negatively affect the timing
Solution Approach 1:
The patent implements a feedback mechanism where the actual propagation delays of clock and command paths are measured during calibration mode, and these measured values are used to adjust the delay circuits. The system continuously monitors and corrects for variations caused by power, voltage, and temperature conditions by comparing actual delay against target delay and making real-time adjustments to compensate for environmental variations.
Solution Approach 2:
The patent makes the delay circuits dynamically adjustable rather than fixed. The delay amount is controlled by adjustable delay circuits that can be programmed based on measured propagation delays. This dynamic adjustment capability allows the system to adapt to changing operating conditions (power, voltage, temperature) by recalibrating the delay values, thereby maintaining timing accuracy across varying environmental conditions.
3Productivity
If memory clock signals operate at high frequency to increase data rate, then productivity improves, but timing alignment between command and clock signals becomes more difficult
Solution Approach 1:
The patent replaces mechanical timing adjustment methods with electronic delay circuits that can be precisely controlled. Instead of relying on physical path length adjustments or mechanical switches, the system uses electronically controlled delay elements whose delay amount can be programmed based on measured propagation delays. This electronic substitution enables precise timing alignment even at high clock frequencies where mechanical adjustment would be insufficient.
Solution Approach 2:
The patent changes the delay parameter of the delay circuits based on measured propagation delays. By measuring the actual delay of clock and command paths and then adjusting the delay circuit parameters accordingly, the system achieves precise timing alignment. This parameter adjustment capability allows the system to maintain correct timing relationships between commands and clock edges even when operating at high frequencies that would make fixed timing designs fail.
Data Source
AI summary
Apparatuses and methods related to altering the timing of command signals for executing commands is disclosed. One such method includes calculating a forward path delay of a clock circuit in terms of a number of clock cycles of an output clock signal provided by the clock circuit and adding a number of additional clock cycles of delay to a forward path delay of a signal path. The forward path delay of the clock circuit is representative of the forward path delay of the signal path and the number of additional clock cycles is based at least in part on the number of clock cycles of forward path delay.