Nonvolatile Memory Signal Layout for Inter-Device Data Sharing

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Solution Overview

Problem

Nonvolatile memory devices sharing information with each other can hinder the operation of a storage device, leading to decreased throughput and suboptimal performance, and may not satisfy communication standards.

Innovation Solution

A storage device design that allows nonvolatile memory devices to communicate information without direct control from the memory controller, using separate signal lines for command and address transmission and data strobe signals, enabling inter-device communication synchronized with data strobe signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If nonvolatile memory devices share information with each other, then information management is improved, but control is hindered and throughput decreases

Engineering Contradiction:
Improveinformation managementVSAvoidthroughput
Core Design Contradiction:
Loss of informationVSProductivity

Solution Approach 1:

The patent segments the communication function by introducing a dedicated information sharing mode that is separate from the normal command execution mode. In this mode, memory devices can exchange information without interfering with the memory controller's control operations, thus resolving the contradiction between information sharing and control efficiency

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements dynamic mode switching where memory devices can transition between normal operation mode and information sharing mode based on operational needs. This allows the system to adaptively balance between information management and throughput requirements without fixed constraints

Inventive Principle:
Principle #15Dynamics

2Loss of information

If nonvolatile memory devices share information with each other, then information management is improved, but communication standard compliance deteriorates

Engineering Contradiction:
Improveinformation managementVSAvoidcommunication standard compliance
Core Design Contradiction:
Loss of informationVSReliability

Solution Approach 1:

The patent introduces the memory controller as an intermediary that manages the information sharing process between memory devices. The controller ensures that information exchange operations comply with communication standards by mediating the interaction protocol, thus maintaining standard compliance while enabling information sharing

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of operation

If memory controller transmits commands and addresses through first signal lines, then control operation is maintained, but inter-device communication is hindered

Engineering Contradiction:
Improvecontrol operationVSAvoidinter-device communication
Core Design Contradiction:
Ease of operationVSAdaptability or versatility

Solution Approach 1:

The patent makes the first signal lines universal by enabling them to serve dual purposes: transmitting commands and addresses from the memory controller during normal operation, and facilitating information exchange between memory devices during information sharing mode. This multi-functionality resolves the contradiction between control operation and inter-device communication

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentEP4693291A1Storage device and operating method of storage device
Publication Date: 2026.02.11 SAMSUNG ELECTRONICS CO LTD
  • EP4693291A1 patent drawingFigure 1
  • EP4693291A1 patent drawingFigure 2
  • EP4693291A1 patent drawingFigure 3

AI summary

There is provided a storage device which includes a plurality of nonvolatile memory devices, and a memory controller connected in common to the plurality of nonvolatile memory devices through first signal lines and connected in common to the plurality of nonvolatile memory devices through second signal lines. Each of the plurality of nonvolatile memory devices receives a command and an address through the first signal lines and communicates data bits with the memory controller through the second signal lines. While the command and the address are not received through the first signal lines, the plurality of nonvolatile memory devices exchange information through the first signal lines without control of the memory controller.