Memory Control Signal Phase Training for Reliable CA Bus Sampling
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Solution Overview
Problem
Existing memory systems face challenges in achieving reliable operation due to misalignment between control signals and clock signals, leading to inconsistent data transmission on the command/address bus.
Innovation Solution
A memory controller adjusts the timing of control signals, such as the clock enable signal (CKE), by sweeping its phase relationship with the rising edge of the clock, allowing it to determine a reliable phase setting that ensures proper data capture on the data bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the control signal is transmitted for a full clock cycle, then the signal stability is improved, but the timing alignment with the clock edge becomes difficult to optimize
Solution Approach 1:
The patent applies dynamics by making the control signal duration variable rather than fixed. The training sequence transmits control signals with different durations (less than full clock cycle) to dynamically adjust and find the optimal timing window that centers the clock edge, thereby achieving both signal stability and precise timing alignment.
Solution Approach 2:
The patent changes the parameter of control signal duration from a fixed full clock cycle to a variable duration less than the full clock cycle. This parameter change enables the system to optimize timing alignment by adjusting the signal width to create a centered window around the clock edge, resolving the contradiction between stability and precision.
2Device complexity
If the phase relationship between control signal and clock signal is fixed, then the system complexity is reduced, but the data transmission reliability deteriorates
Solution Approach 1:
The patent applies preliminary action by performing a training sequence before normal operation. During training, the system pre-determines the optimal phase relationship between control signal and clock signal by testing different phase configurations. This preliminary optimization ensures high data transmission reliability during subsequent normal operation without adding complexity to the main transmission path.
Solution Approach 2:
The system performs self-adjustment through the training sequence, automatically determining the optimal phase relationship without external intervention. The memory device and controller work together to self-calibrate the timing parameters, achieving reliable data transmission while keeping the system design simple.
3Reliability
If the control signal activation window is widened, then the margin for timing errors is improved, but the precision of data sampling is reduced
Solution Approach 1:
The patent uses dynamics by implementing a training sequence that tests different control signal durations. The system dynamically identifies the optimal window width that provides sufficient timing error margin while maintaining precise data sampling. This dynamic optimization resolves the contradiction by finding the specific window width that balances both requirements.
Solution Approach 2:
The patent applies partial action by using a control signal duration that is less than the full clock cycle. This partial duration creates an optimized activation window that provides timing error margin while maintaining sampling precision, avoiding the excessive action of using the full clock cycle which would reduce precision.
Data Source
AI summary
A controller iteratively activates a control signal for one-half a clock cycle while sweeping its phase relationship to the rising edge of the clock. Phase relationships that result in the rising edge of the clock occurring while the control signal is active result in the memory device outputting command/address data on the data bus. Phase relationships that do not result in the rising edge of the clock occurring while the control signal is active do not result in the memory device outputting the command/address data on the data bus. By changing the data on the CA bus between activations of the control signal, the controller can ascertain what phase relationships result in the control signal being successfully sampled. From this information, the controller can select a reliable setting for the phase relationship between the control signal and the clock signal.