On-Die Memory Signal Processing for Low-Power Multi-Threshold Reads
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Solution Overview
Problem
Existing memory devices face inefficiencies in data storage and retrieval due to the need for high-speed interfaces that often result in high power consumption and increased complexity, particularly when performing signal processing tasks like error correction and interference cancellation, which require large data transfers between semiconductor dies.
Innovation Solution
The implementation of an internal signal processing unit on the same semiconductor die as the memory array, which performs preprocessing tasks such as multiple read operations using different thresholds, computes soft metrics, and cancels interference, reducing the data transferred to an external memory controller and minimizing latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If signal processing tasks (error correction, interference cancellation) are performed by transferring large data amounts between semiconductor dies, then data processing capability is improved, but power consumption increases and device complexity increases
Solution Approach 1:
The patent merges the signal processing unit with the memory array by fabricating both on the same semiconductor die. This integration eliminates the need for high-speed data transfers between separate dies, thereby reducing power consumption while maintaining data processing capability. The processing unit directly accesses memory cells through internal circuitry rather than external interfaces.
Solution Approach 2:
The patent introduces an intermediate buffer memory located on the same die as the memory array. This buffer serves as a mediator that allows the signal processing unit to access and process memory data without requiring high-speed external data transfers, thus reducing power consumption while enabling complex signal processing operations.
2Productivity
If signal processing tasks are performed by transferring large data amounts between semiconductor dies, then data processing capability is improved, but device complexity increases
Solution Approach 1:
The patent combines the signal processing unit and memory array on a single semiconductor die, reducing device complexity by eliminating the need for complex high-speed external interfaces and inter-die communication infrastructure. The integrated design simplifies the overall system architecture while maintaining full data processing capability.
3Speed
If high-speed interfaces are used for data transfer between semiconductor dies, then data throughput is improved, but power dissipation increases
Solution Approach 1:
The patent integrates the signal processing unit on the same die as the memory array, eliminating high-speed external interfaces and their associated power dissipation. Data processing occurs through internal low-power circuitry, maintaining data throughput while significantly reducing power loss.
4Measurement precision
If data is read multiple times with different thresholds for preprocessing, then measurement precision is improved, but loss of time increases
Solution Approach 1:
The patent performs preliminary signal processing operations including multiple threshold reads and interference cancellation directly within the memory device before data transfer. This preliminary action ensures high measurement precision is achieved through thorough processing, while the integrated architecture minimizes the time penalty by performing these operations in parallel and using low-speed interfaces only for final data transfer.
Data Source
AI summary
A method for operating a memory includes storing data in a plurality of analog memory cells that are fabricated on a first semiconductor die by writing input storage values to a group of the analog memory cells. After storing the data, multiple output storage values are read from each of the analog memory cells in the group using respective, different threshold sets of read thresholds, thus providing multiple output sets of the output storage values corresponding respectively to the threshold sets. The multiple output sets of the output storage values are preprocessed by circuitry that is fabricated on the first semiconductor die, to produce preprocessed data. The preprocessed data is provided to a memory controller, which is fabricated on a second semiconductor die that is different from the first semiconductor die. so as to enable the memory controller to reconstruct the data responsively to the preprocessed data.