Memory Signal Transmission Circuit Modeling for PVT Synchronization
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Solution Overview
Problem
Signal transmission in semiconductor memory devices is affected by process, voltage, and temperature variations, leading to desynchronization of data and clock signals.
Innovation Solution
A signal transmission circuit is designed with data transmission circuits modeled on clock transmission circuits, ensuring synchronization by applying power supply and ground voltages to differential input nodes, thereby minimizing the influence of PVT variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data transmission circuits are used to transmit data signals, then data transmission function is achieved, but synchronization with clock signals deteriorates due to PVT variations
Solution Approach 1:
The patent applies the copying principle by creating a clock transmission circuit that is an identical copy of the data transmission circuit. Both circuits use the same differential sensing and amplification structure, ensuring that they respond identically to PVT variations. This copying approach allows the clock signal to be transmitted through the same pathway as data signals, guaranteeing synchronized transmission without additional synchronization complexity.
Solution Approach 2:
The patent implements universality by designing a single circuit structure that serves dual purposes: the data transmission circuit transmits data signals while the identical clock transmission circuit transmits clock signals. Both functions share the same differential input node pair architecture, sensing mechanism, and amplification pathway, eliminating the need for separate dedicated clock transmission infrastructure and ensuring uniform PVT response for both signal types.
2Reliability
If separate clock transmission path is used, then clock signal transmission is achieved, but synchronization with data signals deteriorates
Solution Approach 1:
The patent merges the clock transmission function into the data transmission circuit by using the exact same differential input node pair, sensing circuitry, and amplification pathway for both data and clock signals. This consolidation eliminates the need for separate dedicated clock transmission lines and components, reducing overall device complexity while maintaining perfect synchronization through identical signal processing for both data and clock.
Solution Approach 2:
The data transmission circuit is designed with universal functionality to handle both data signals and clock signals through its identical differential sensing and amplification structure. The clock transmission circuit is another identical copy that processes clock signals through the same mechanism, ensuring that both signal types experience the same transmission characteristics and PVT variations, thereby simplifying the overall transmission path architecture.
3Device complexity
If data transmission circuit structure is used for clock transmission, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses copying to create an identical replica of the data transmission circuit for clock transmission purposes. Both circuits share the same differential input node pair configuration, sensing transistor arrangement, and amplification stages. This copying approach simplifies device complexity by reusing the same proven structure, while the manufacturing precision requirements are managed through standard differential pair design techniques that inherently compensate for mismatches through common-mode rejection.
Solution Approach 2:
The patent applies homogeneity by using identical circuit topologies for both data and clock transmission paths. The differential input node pairs, sensing circuits, and amplifiers are constructed with the same components and geometry. This homogeneous design reduces device complexity through reuse while managing manufacturing precision through matched component selection and differential signaling that naturally rejects common-mode variations, making the system robust to manufacturing tolerances.
Data Source
AI summary
A signal transmission circuit comprising: a first data transmission circuit configured to output, through a first data output node thereof and in response to a first operation clock applied to a first clock input node thereof, first output data obtained by sensing and amplifying a first input data pair applied to a first differential input node pair thereof, a clock transmission circuit configured to output through a second data output node thereof, a second operation clock generated in response to the first operation clock applied to a second clock input node thereof while a power supply voltage and a ground voltage are applied to a second differential input node pair thereof, and a first data output circuit configured to output the first output data in synchronization with the second operation clock, wherein the first data transmission circuit is modeled on the clock transmission circuit.