Memory Array Sign-Bit Decoding for Lower Keeper Current
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Solution Overview
Problem
In memory devices, excessive keeper current degrades access time and low level read margin due to bit line leakage current, particularly in columns with varying on-bit ratios.
Innovation Solution
Implementing a keeper circuit with sign bits to flip specific rows of the memory array, narrowing the distribution of bit-line leakage current and optimizing on-bit ratios, thereby reducing keeper current and improving access time and read margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a keeper circuit is coupled with each bit line to hold high bit line level against bit line leakage current, then high level sensing is improved, but access time is degraded and low level read margin is reduced due to excessive keeper current
Solution Approach 1:
The patent applies local quality by differentiating keeper circuit configurations across different columns based on their specific on-bit ratios. Columns with higher on-bit ratios use different keeper current settings than columns with lower on-bit ratios, optimizing performance for each local condition rather than using a uniform approach across all columns.
Solution Approach 2:
The patent changes the keeper current parameter dynamically or selectively across different columns to match their specific leakage characteristics. By adjusting the keeper current parameter based on measured or predetermined on-bit ratios, the system achieves optimal balance between maintaining high bit line levels and minimizing access time degradation.
2Reliability
If a keeper circuit is coupled with each bit line to hold high bit line level against bit line leakage current, then high level sensing is improved, but low level read margin is degraded due to excessive keeper current
Solution Approach 1:
The patent implements local quality by configuring keeper circuits with different current levels in different columns based on their specific on-bit ratio characteristics. This localized optimization ensures that each column's keeper current is tailored to its specific leakage profile, preserving low level read margin while maintaining high level sensing capability.
Solution Approach 2:
The patent modifies the keeper current parameter selectively across columns to match their specific leakage characteristics. By changing this electrical parameter based on measured performance or predetermined design criteria, the system optimizes both high level sensing and low level read margin simultaneously.
3Productivity
If columns have varying on-bit ratios, then memory array utilization is improved, but bit line leakage current distribution widens requiring higher keeper current
Solution Approach 1:
The patent applies local quality by measuring or determining the on-bit ratio for each column and configuring the keeper circuit in that specific column according to its unique characteristics. This column-specific optimization allows high memory array utilization while preventing excessive keeper current by matching each column's keeper current to its specific leakage profile.
Solution Approach 2:
The patent changes the keeper current parameter on a column-by-column basis according to measured or predetermined on-bit ratios. This selective parameter adjustment enables the system to accommodate varying memory array utilization patterns without requiring uniformly high keeper current across all columns.
Data Source
AI summary
A memory device includes a first memory column, a memory array and a sign decoder. The first memory column is configured to store first sign bits. The memory array is configured to store a first data array and generate bit line signals. The sign decoder is configured to output data signals according to the first sign bits and the bit line signals. The data signals correspond to a second data array, and the first data array is generated by reversing rows of the second data array according to the first sign bits.