Memory Device Metal Silicide Uniformity Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The manufacturing process of flash memory faces challenges in controlling the uniformity of the metal silicide layer, leading to low yield and poor reliability due to difficulties in achieving consistent resistance in word lines.
Innovation Solution
A memory device structure is formed with a stack of conductive layers, including a barrier layer between the metal silicide and the second conductive layer, and a dielectric layer that laterally surrounds the stack structures to expose a portion of the metal silicide, allowing for uniform metal silicidation and improved resistance uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a metal silicide layer is formed to reduce the resistance of word lines, then the electrical conductivity is improved, but the uniformity of the metal silicide layer becomes difficult to control
Solution Approach 1:
The patent divides the metal silicide formation process into multiple controlled stages: first forming a metal layer, then performing a first silicidation process to create a high-resistance metal silicide, followed by a second silicidation process to transform it into a low-resistance metal silicide. This segmentation allows precise control over the uniformity and resistance characteristics of the final metal silicide layer.
Solution Approach 2:
The patent performs preliminary actions by first forming a metal layer and then transforming it into a high-resistance metal silicide before finalizing it as a low-resistance metal silicide. This preliminary transformation sequence ensures that the metal silicide layer achieves uniform formation and proper electrical characteristics before being integrated into the memory device.
2Length of moving object
If the critical size of flash memory is reduced to achieve lightness and compact size, then the device dimensions are improved, but the manufacturing process faces challenges leading to low yield
Solution Approach 1:
The patent applies local quality by forming a dielectric layer that laterally surrounds the lower portion of stack structures, selectively exposing specific portions of the metal silicide layer. This localized structural arrangement enables precise control over electrical connections at different locations, ensuring consistent performance even as device dimensions shrink.
Solution Approach 2:
The patent introduces a lateral dimension control mechanism by using a dielectric layer that laterally surrounds stack structures. This dimensional approach allows precise control over the exposure and connection of metal silicide portions, maintaining manufacturing yield while reducing overall device size.
3Reliability
If the metal silicide layer uniformity is not controlled, then the resistance of word lines becomes inconsistent, but controlling it requires complex manufacturing processes
Solution Approach 1:
The patent utilizes parameter changes by performing multiple silicidation processes with different conditions to transform the metal layer into high-resistance and then low-resistance metal silicide. This controlled parameter transformation ensures consistent resistance characteristics across the metal silicide layer without requiring overly complex manufacturing processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the uniformity of the resistance of word lines, thereby increasing the reliability and yield of the memory device by ensuring consistent metal silicide layer formation across the device.
Implementation Method 1
performing a metal silicidation process to transform the third conductive layer into a metal silicide layer
Data Source
AI summary
Provided is a memory device including a plurality of stack structures disposed on a substrate; and a dielectric layer. Each stack structure includes a first conductive layer, a second conductive layer, an inter-gate dielectric layer, a metal silicide layer, and a barrier layer. The second conductive layer is disposed on the first conductive layer. The inter-gate dielectric layer is disposed between the first and second conductive layers. The metal silicide layer is disposed on the second conductive layer. The barrier layer is disposed between the metal silicide layer and the second conductive layer. The dielectric layer laterally surrounds a lower portion of the plurality of stack structures to expose a portion of the metal silicide layer of the plurality of stack structures.