3D Memory Control Gate Silicide Shorts Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for increasing memory storage capacity in LSI devices face challenges due to difficulties in micropatterning, leading to proposals for three-dimensionally laminated memories, but these face issues with shorts and leakage currents due to the formation of silicide layers on control gates.
Innovation Solution
The solution involves forming nonvolatile semiconductor memory devices with a structure where the surfaces of inter-electrode insulating films project more than the control gates in the slit, preventing shorts by increasing the distance between control gates and forming silicide layers only on the control gates, not on the inter-electrode insulating films, and providing unevenness at the interfaces between films to enhance surface area exposure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If three-dimensionally laminated memory is manufactured by collectively processing memory layers, then storage capacity is increased, but shorts and leakage currents occur due to silicide layer formation on control gates
Solution Approach 1:
The patent applies local quality by making the inter-electrode insulating film thicker at specific locations (below control gates in the slit) compared to other areas. This localized thickness variation prevents silicide layer formation on control gates while maintaining normal insulating film structure elsewhere, thereby eliminating shorts and leakage currents without compromising the three-dimensional laminated memory structure
Solution Approach 2:
The patent introduces an intermediary structure (the slit with uneven insulating film thickness) between the control gates to prevent direct contact and electrical shorts. The thicker insulating film in the slit region acts as a mediator that isolates adjacent control gates, preventing leakage currents while allowing the memory device to function properly
2Quantity of substance
If micropatterning is used to increase storage capacity, then element size is reduced, but manufacturing difficulty and cost increase
Solution Approach 1:
The patent transitions from two-dimensional planar memory to three-dimensional laminated memory by stacking multiple memory layers vertically. This dimensional change allows storage capacity to increase without requiring further micropatterning of individual elements, thereby avoiding the associated manufacturing difficulties and cost increases
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device comprises a first conductive layer, a second conductive layer, a first inter-electrode insulating film, and a third conductive layer stacked above the first conductive layer, a memory film, a semiconductor layer, an insulating member, and a silicide layer. The memory film and the semiconductor layer is formed on the inner surface of through hole provided in the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The insulating member is buried in a slit dividing the second conductive layer, the first inter-electrode insulating film, and the third conductive layer. The silicide layer is formed on surfaces of the second conductive layer and the third conductive layer in the slit. The distance between the second conductive layer and the third conductive layer along the inner surface of the slit is longer than that of along the stacking direction.