3D Memory Strings with Silicon Germanium Select Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor memory devices face challenges in miniaturization due to increasing costs and physical limitations, such as withstand voltage issues, which hinder device operation and integration density.
Innovation Solution
A nonvolatile semiconductor memory device with a three-dimensional configuration, featuring memory strings with columnar semiconductor layers and charge storage layers, and select transistors with silicon germanium layers, which improve integration density and reduce contact resistance through crystallization and specific manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If amorphous silicon is crystallized to form columnar semiconductor layers, then the semiconductor structure is formed, but the crystals become minute and cell current increases, hindering memory speed improvement
Solution Approach 1:
The patent changes the crystallization parameters by introducing silicon germanium layers with specific germanium concentrations (5-30 at%) and controlling crystallization temperature (500-600°C) and time (1-24 hours) to achieve larger crystal grains and reduce cell current
Solution Approach 2:
The patent uses composite material structure combining silicon germanium layers with amorphous silicon layers, where the silicon germanium acts as a crystallization catalyst to promote grain growth and improve memory performance
2Quantity of substance
If three-dimensional memory structure is implemented, then integration density increases, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory structure to three-dimensional vertical structure by forming columnar semiconductor layers extending perpendicular to the substrate, enabling higher integration density
Solution Approach 2:
The patent divides the memory structure into multiple segments including memory strings with select transistors, charge storage layers, and columnar semiconductor layers, allowing modular manufacturing and reducing overall process complexity
3Quantity of substance
If conventional miniaturization is pursued, then storage capacity increases, but lithographic costs increase and physical limitations are encountered
Solution Approach 1:
The patent achieves higher storage capacity by extending memory structures in the vertical dimension rather than reducing lateral dimensions, avoiding the need for advanced lithographic processes and associated cost increases
Solution Approach 2:
The patent changes the scaling approach from lateral miniaturization to vertical expansion by forming tall columnar semiconductor layers and stacking multiple memory strings, thereby increasing capacity without encountering lithographic physical limitations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a high degree of integration, reduces contact resistance, and enhances cell current performance, overcoming the limitations of miniaturization and cost constraints in existing technologies.
Implementation Method 1
the columnar semiconductor layer is constituted by polysilicon and formed from amorphous silicon by subjecting the amorphous silicon to crystallization heat treatment
Implementation Method 2
a third semiconductor layer formed on an upper surface of the second semiconductor layer and including silicon germanium
Data Source
AI summary
A memory string comprises: a first semiconductor layer having a plurality of columnar portions extending in a perpendicular direction with respect to a substrate, and joining portions joining lower ends of the plurality of columnar portions; a charge storage layer surrounding a side surface of the first semiconductor layer; and a first conductive layer surrounding a side surface of the charge storage layer and functioning as a control electrode of memory cells. A select transistor comprises: a second semiconductor layer extending upwardly from an upper surface of the columnar portions; an insulating layer surrounding a side surface of the second semiconductor layer; a second conductive layer surrounding a side surface of the insulating layer and functioning as a control electrode of the select transistors; and a third semiconductor layer formed on an upper surface of the second semiconductor layer and including silicon germanium.