Nonvolatile Memory Impedance Calibration
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Solution Overview
Problem
Semiconductor memory devices face challenges in impedance calibration, particularly in non-volatile memory devices where impedance variations due to temperature, voltage, and component drift affect performance, making it difficult to efficiently perform operations like read, program, and erase without interfering with the calibration process.
Innovation Solution
An operating method and device architecture that simultaneously perform impedance calibration operations with read, program, or erase operations by using a control logic to detect command sequences and activate an impedance calibration circuit with an external reference resistor, ensuring calibration occurs during busy periods without impacting data operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If impedance calibration is performed separately from data operations, then calibration accuracy is improved, but total operation time increases
Solution Approach 1:
The patent combines impedance calibration operations with data operations (read, program, erase) into a single integrated process. The calibration circuit and data operation circuits share common resources and time slots, allowing both functions to be performed simultaneously without requiring separate calibration cycles, thereby reducing total operation time while maintaining calibration accuracy.
Solution Approach 2:
The patent enables continuous operation by performing impedance calibration during the execution of data operations rather than pausing data operations to perform calibration. The calibration process is embedded within the operational flow, ensuring that the calibration function continues to operate without interruption while data operations proceed normally.
2Productivity
If impedance calibration is performed during busy periods, then productivity is improved, but device complexity increases
Solution Approach 1:
The patent designs the calibration circuit and control logic to serve multiple functions: performing impedance calibration, monitoring operation status, and coordinating with data operation circuits. This multi-functional approach allows the same hardware resources to be reused for both calibration and data operations, reducing the need for additional dedicated components and managing complexity through resource sharing.
Solution Approach 2:
The patent implements dynamic control where the calibration process adapts its timing and resource allocation based on the current operational state of the device. The control logic dynamically schedules calibration operations during idle or less critical time slots within busy periods, adjusting the calibration intensity and duration according to real-time system conditions to balance productivity gains with complexity management.
Data Source
AI summary
An operating method of a nonvolatile memory device is provided which includes receiving a command sequence; detecting whether the input command sequence accompanies an impedance calibration operation; and if the input command sequence accompanies the impedance calibration operation, simultaneously performing an operation corresponding to the input command sequence and the impedance calibration operation.