3D Memory Timing Skew Calibration via Phase Comparison
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Solution Overview
Problem
In memory devices using 3D layout technology, timing skew between stacked memory chips leads to inefficiencies in data transmission, as the phase differences in data received through different through-silicon via channels cause delays, affecting the integration and capacity of semiconductor chips.
Innovation Solution
A method is implemented where a master chip instructs first and second memory chips to perform read operations, transfers data through specific channels, compares the phases of data received, and adjusts the delay value of the data transmission channels to minimize timing skew by calibrating the data transmission timing between the chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple memory chips are stacked using 3D layout technology, then integration and capacity are improved, but timing skew between chips causes data transmission delays
Solution Approach 1:
The patent performs phase calibration before normal data transmission operations. The master chip executes a calibration routine that measures phase differences between stacked memory chips and pre-adjusts timing parameters, so that when actual data transmission occurs, the timing skew has already been compensated, eliminating delays without affecting operational speed
Solution Approach 2:
The patent implements a feedback mechanism where the master chip continuously monitors phase differences between data signals from different memory chips through dedicated phase detection circuits. Based on this feedback, the system dynamically adjusts timing skew compensation parameters to maintain synchronized data transmission across all stacked chips
2Speed
If through-silicon via channels are used for data transmission, then transmission speed is improved, but phase differences in data received through different channels cause timing skew
Solution Approach 1:
The patent applies different timing compensation parameters to different through-silicon via channels based on their individual characteristics. Each channel is calibrated separately to account for variations in physical path length and signal propagation characteristics, allowing high-speed transmission through each channel while maintaining overall timing synchronization through localized timing adjustments
Data Source
AI summary
An operating method of a memory device includes: instructing, by a master chip, a first memory chip and a second memory chip to perform a read operation; transferring, by the first memory chip, data stored in the first memory chip to the master chip through a first through-chip channel in response to the read operation instruction, and transferring, by the second memory chip, data stored in the second memory chip to the master chip through a second through-chip channel in response to the read operation instruction; comparing, by the master chip, a phase of the data transferred through the first through-chip channel with a phase of the data transferred through the second through-chip channel; and adjusting a delay value of a data transmission channel of at least one of the first memory chip and the second memory chip based on a result of the comparing.