Memory Device Skip Calculation Mode for Invalid Data
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Solution Overview
Problem
Memory bandwidth and latency issues in stacked semiconductor systems lead to inefficiencies and increased power consumption due to inter-device communication penalties during multiple accesses.
Innovation Solution
A memory device and method that implement a skip calculation mode, where processing circuitry on semiconductor dies selectively performs calculations based on index data indicating valid or invalid internal data, omitting unnecessary operations and reducing power consumption by bypassing invalid data processing and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple accesses are performed to stacked memory device, then memory capacity is increased, but inter-device bandwidth and latency penalties increase
Solution Approach 1:
The patent combines multiple memory die into a stacked configuration where multiple memory banks are vertically integrated. This merging allows simultaneous access to multiple memory banks through a single interface, increasing effective memory capacity while reducing the time penalty of sequential accesses by enabling parallel operation across stacked die.
Solution Approach 2:
The patent transitions from a two-dimensional memory expansion approach to a three-dimensional stacked architecture. By adding the vertical dimension through multiple stacked die connected via TSVs, the system achieves increased memory capacity without proportionally increasing inter-device communication latency, as the stacking enables parallel access paths.
2Quantity of substance
If multiple accesses are performed to stacked memory device, then memory capacity is increased, but inter-device bandwidth penalties increase
Solution Approach 1:
The stacked memory architecture merges multiple memory die into a unified system where data can be accessed in parallel across banks. This reduces the total bandwidth required for multiple accesses compared to sequential access in non-stacked configurations, thereby reducing energy consumption associated with bandwidth penalties.
Solution Approach 2:
The patent enables continuous parallel access operations across multiple stacked memory banks. By maintaining simultaneous read/write operations across different banks through the unified interface, the system maximizes useful action continuity and minimizes idle bandwidth periods, reducing energy waste from bandwidth penalties.
3Reliability
If calculations are performed on all data including invalid data, then processing completeness is maintained, but power consumption increases
Solution Approach 1:
The patent extracts and identifies invalid data using index data that marks the validity status of each data element. By separating valid data from invalid data through the index mechanism, the system performs calculations only on valid data, eliminating wasted power consumption on invalid data while maintaining processing completeness for all valid elements.
Solution Approach 2:
Instead of performing calculations on all data (excessive action), the patent applies partial action by selectively processing only valid data identified through index data. This partial processing approach reduces power consumption while maintaining sufficient processing completeness for all meaningful data elements.
Data Source
AI summary
A memory device includes a memory cell array formed in a semiconductor die, the memory cell array including a plurality of memory cells to store data and a calculation circuit formed in the semiconductor die. The calculation circuit performs calculations based on broadcast data and internal data and omits the calculations with respect to invalid data and performs the calculations with respect to valid data based on index data in a skip calculation mode, where the broadcast data are provided from outside the semiconductor die, the internal data are read from the memory cell array, and the index data indicates whether the internal data are the valid data or the invalid data. Power consumption is reduced by omitting the calculations and the read operation with respect to the invalid data through the skip calculation mode based on the index data.