Memory Unit Sleep Switching for Low-Power Data Retention
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Solution Overview
Problem
Volatile memory consumes power even when not in use, leading to static power consumption and data loss upon power interruption.
Innovation Solution
A memory system with configurable memory units that switch between active (RUN) and power-saving (SLEEP) modes, using controllable switches to power peripheral circuits only when needed, managed by a controller that tracks access times and configures units based on inactivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the volatile memory remains permanently powered to prevent data loss, then data integrity is maintained, but static power consumption increases for unused memory portions
Solution Approach 1:
The memory is divided into multiple independently controllable memory units (e.g., banks or blocks), each with its own peripheral circuit. The controller can selectively power down individual memory units that are not currently being accessed, while keeping only the actively used units powered on. This segmentation allows granular power management, reducing overall static power consumption without compromising data integrity in the powered-on units.
Solution Approach 2:
The power state of memory units is made dynamic rather than static. The controller continuously monitors access patterns and dynamically adjusts the power state of memory units between active and powered-down states based on current usage requirements. This dynamic adaptation ensures that memory units consume power only when necessary, eliminating wasteful static power consumption while maintaining data integrity through proper state management.
2Use of energy by stationary object
If the peripheral circuit is powered down to save energy, then power consumption decreases, but access to memory cells becomes impossible
Solution Approach 1:
Before powering down a memory unit, the controller performs preliminary actions to ensure future accessibility. This includes detecting that the memory unit has not been accessed for a predetermined time period, then safely transitioning it to a powered-down state. The controller maintains the ability to rapidly reactivate the peripheral circuit when needed, ensuring that memory access capability is restored immediately upon new access requests without data loss.
Solution Approach 2:
The system implements feedback mechanisms where the controller monitors access patterns to memory units and uses this information to make informed power management decisions. When the controller detects that a memory unit has not been accessed for a predetermined time period, it automatically transitions the peripheral circuit to a powered-off state. This feedback-driven approach ensures that memory units are powered down only when truly inactive, maintaining full access capability when needed while minimizing power consumption during idle periods.
Data Source
AI summary
A system includes a memory formed by memory units accessible in write mode and in read mode. Each memory unit includes an array of memory cells and a peripheral circuit of access to the memory cells. Each memory unit is configurable in a first operating mode and a second operating mode. The array of memory cells are set in the first operating mode and the second operating modes to retain data until a subsequent powering off of the memory unit. The peripheral circuit is powered in the first operating mode and is not powered in the second operating mode. A controller configures any memory unit of the memory having undergone no write or read access for a determined time period to be in the second operating mode.