Memory Device Sleep-Mode Management for Low Standby Current

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Solution Overview

Problem

Conventional memory sub-systems experience inefficiencies and performance issues due to frequent transitions between active and sleep modes, leading to increased power consumption, command response time delays, and reduced endurance, primarily caused by high standby currents and power supply cycling during sleep mode operations.

Innovation Solution

Implementing a low power mode management component that supplies a reference voltage to the voltage regulator, powers down the bandgap circuit, and maintains the power supply on, reducing standby current consumption to 5 μA or less and minimizing entry and exit latencies during sleep mode transitions.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the memory sub-system transitions to sleep mode to reduce power consumption, then power consumption is reduced, but command response time increases due to entry and exit latencies

Engineering Contradiction:

Improvepower consumptionVSAvoidcommand response time

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent implements dynamic power management by transitioning the memory sub-system between active and sleep modes based on workload conditions. The low power mode management component dynamically controls the voltage regulator to adjust output voltage levels, enabling the system to adapt its power consumption and performance characteristics to match actual operational needs, thereby resolving the contradiction between power savings and response time.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameter supplied to the voltage regulator based on operational mode. During sleep mode transitions, the system adjusts the reference voltage level to optimize the balance between power consumption and exit latency. By modifying voltage parameters dynamically, the system achieves faster wake-up times while maintaining low power consumption during idle periods.

Inventive Principle:

Principle #35Parameter changes

2Use of energy by moving object

If the memory sub-system frequently transitions between active and sleep modes, then power consumption is reduced during idle periods, but endurance is reduced due to power supply cycling

Engineering Contradiction:

Improvepower consumptionVSAvoidendurance

Core Design Contradiction:

Use of energy by moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by maintaining the power supply in an on state even during sleep mode operations. The low power mode management component prepares the voltage regulator by keeping it configured and ready, so that when the system needs to wake up, no power supply cycling is required. This preliminary preparation eliminates the wear caused by frequent power cycles while still achieving power savings through reduced voltage output.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent segments the power management functions by separating the power supply control from the voltage regulation control. The power supply remains continuously on while the voltage regulator's output is dynamically adjusted. This segmentation allows the system to achieve low power consumption through voltage control without subjecting the power supply to frequent cycling, thereby preserving endurance.

Inventive Principle:

Principle #1Segmentation

3Reliability

If the voltage regulator supplies normal voltage levels during sleep mode, then data reliability is maintained, but standby current consumption increases

Engineering Contradiction:

Improvedata reliabilityVSAvoidstandby current consumption

Core Design Contradiction:

ReliabilityVSLoss of energy

Solution Approach 1:

The patent changes the voltage parameter supplied to the voltage regulator based on operational mode. During sleep mode, the system adjusts the reference voltage level to optimize the balance between power consumption and data reliability. By modifying voltage parameters dynamically, the system achieves lower standby current while maintaining sufficient voltage levels to preserve data integrity in non-volatile memory.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies different voltage quality levels to different operational states. During active mode, full voltage levels are supplied for optimal performance and reliability. During sleep mode, reduced voltage levels are supplied specifically to the voltage regulator output, which is sufficient to maintain data reliability in non-volatile memory while significantly reducing standby current consumption. This local differentiation of voltage quality resolves the contradiction.

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS12417804B2Low power management for sleep mode operation of a memory device

Publication Date: 2025.09.16 MICRON TECHNOLOGY INC

AI summary

In a memory sub-system, causing a standby circuit associated with a memory device to enter into a low power mode. In the low power mode, causing a reference voltage to be supplied to a voltage regulator, wherein the reference voltage causes the voltage regulator to supply a standby current level to the memory device, where the standby current level is lower than a current level supplied when the memory device is in an active mode.