Memory System Sleep-State Control for Lower Idle Power

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Solution Overview

Problem

Existing memory systems face challenges in reducing power consumption across different usage scenarios, particularly when there is no data transmission with the host, leading to increased power consumption and reduced standby time.

Innovation Solution

The memory system incorporates a memory controller that controls sequential transitions between activation modes and sleep modes, including an idle mode and first and second sleep modes, with power consumption decreasing from activation mode to sleep mode, and further reducing power by cutting off supplies in deeper sleep modes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the memory system maintains data transmission state continuously, then the response speed to host demands is improved, but the power consumption increases significantly during idle periods

Engineering Contradiction:
Improveresponse speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The memory controller dynamically adjusts the operating state of the memory system based on activity detection. When no data transmission is detected with the host, the system transitions from an active data transmission state to a sleep mode, reducing power consumption while maintaining the capability to quickly resume data transmission when needed.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes operational parameters by switching between different power modes. The memory controller modifies the power state of the memory system from full operational mode during data transmission to reduced power mode during idle periods, thereby optimizing the balance between response speed and power consumption.

Inventive Principle:
Principle #35Parameter changes

2Use of energy by moving object

If the memory system enters deep sleep mode to reduce power consumption, then the power consumption decreases, but the response delay increases

Engineering Contradiction:
Improvepower consumptionVSAvoidresponse delay
Core Design Contradiction:
Use of energy by moving objectVSLoss of time

Solution Approach 1:

The memory controller performs preliminary actions by detecting idle conditions and transitioning the memory system to sleep mode in advance before actual data transmission is needed. This proactive approach allows the system to be already in a low-power state when idle, and可以快速 transition back to active mode when data transmission is required, minimizing the perceived response delay.

Inventive Principle:
Principle #10Preliminary action

3Use of energy by moving object

If the memory system uses multiple sleep modes with different power levels, then the power consumption optimization is improved, but the control complexity increases

Engineering Contradiction:
Improvepower consumption optimizationVSAvoidcontrol complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The sleep mode is segmented into different depth levels (first sleep mode and second sleep mode) with progressively lower power consumption. The memory controller can select appropriate sleep depth based on the duration and nature of idle periods, allowing fine-grained power optimization without requiring complex control logic for each individual component.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250216925A1Memory system and operation method thereof and power management module
Publication Date: 2025.07.03 YANGTZE MEMORY TECH CO LTD
  • US20250216925A1 patent drawing
  • US20250216925A1 patent drawing
  • US20250216925A1 patent drawing

AI summary

A memory system includes at least one memory device and a memory controller coupled with the at least one memory device. The memory controller is configured to control the memory system to enter a first activation mode and a transition mode sequentially, and control the memory system to maintain in the transition mode for a first period of time. The transition mode includes an idle mode and a first sleep mode. A power of the memory system in the first sleep mode is less than a power of the memory system in the idle mode. The power of the memory system in the idle mode is less than a power of the memory system in the first activation mode.