Dynamic Memory Slice Allocation for Buffer Width and Power Control
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Solution Overview
Problem
Existing memory devices face a trade-off between power consumption and memory capacity, with reducing memory size leading to insufficient capacity and increasing size increasing power consumption.
Innovation Solution
Implementing a method for dynamic buffer width allocation by using a memory with multiple memory slices, selectively activating and deactivating slices based on current arithmetic operations to adapt buffer size, and utilizing logic to manage slice activation and deactivation for optimized power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If memory size is reduced to lower power consumption, then power consumption decreases, but memory capacity becomes insufficient
Solution Approach 1:
The memory device is divided into multiple independently controllable memory slices (first memory slice, second memory slice, etc.), each capable of being selectively activated or deactivated. This segmentation allows the system to allocate only the necessary memory capacity for current operations while keeping other slices inactive, thereby reducing power consumption without permanently reducing total memory capacity.
Solution Approach 2:
The memory allocation system dynamically adjusts the number of active memory slices based on the buffer width requirements of ongoing arithmetic operations. The control logic continuously monitors operational needs and activates or deactivates slices in real-time, transforming the static memory configuration into a dynamic one that adapts to changing demands, thus optimizing the balance between power consumption and memory capacity.
2Quantity of substance
If memory size is increased to provide sufficient capacity, then memory capacity increases, but power consumption increases
Solution Approach 1:
By segmenting the memory into multiple slices, the system can provide large total memory capacity while only activating the necessary portion for current operations. The inactive slices consume minimal power, effectively decoupling total memory capacity from active power consumption.
Solution Approach 2:
Different memory slices can be in different states (active or inactive) simultaneously, allowing local optimization of power consumption. The control logic applies different quality states to different parts of the memory system based on local operational requirements, rather than uniformly managing the entire memory space.
3Device complexity
If fixed memory width is used to simplify design, then device complexity decreases, but adaptability to different operational needs decreases
Solution Approach 1:
The system transitions from a fixed memory width configuration to a dynamic one where the buffer width can be adjusted by activating different combinations of memory slices. This dynamic approach maintains relatively simple control logic while significantly improving adaptability to different arithmetic operation requirements.
Solution Approach 2:
The same set of memory slices can serve multiple different buffer width requirements by being selectively activated or deactivated. This multi-functional design allows a single memory structure to adapt to various operational needs without requiring separate dedicated memory blocks for each possible buffer width.
Data Source
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AI summary
The present disclosure refers to a method for dynamic buffer width allocation, that provides a memory with a plurality of memory slices, determines a buffer width for a set of arithmetic operations, allocates a number of memory slices of the plurality of memory slices, the number of memory slices forming a buffer having at least the determined buffer width, and performs the set of arithmetic operations using the buffer. Furthermore, a dynamic memory with a plurality of memory slices and an apparatus are described.