3D Memory Slit Structure for Etch Damage Reduction
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving high performance and reliability due to limitations in the design and manufacturing processes of semiconductor devices, particularly in the arrangement and integration of memory cells and conductive patterns.
Innovation Solution
The semiconductor device incorporates a pipe gate with a pipe channel film, source-side, and drain-side channel films, alternately stacked interlayer insulation films, and conductive patterns, with a slit between the channel films to divide the stacks, and uses a method involving the formation of a preliminary structure with sacrificial films and conductive patterns to enhance performance and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional three-dimensional memory device design is used, then integration density is achieved, but performance and reliability are insufficient due to etch-induced damage and electric field concentration
Solution Approach 1:
The patent introduces a slit structure that divides the continuous channel film into separate segments (first channel film and second channel film). This segmentation prevents etch-induced damage from affecting the entire channel continuously, isolating damage to specific regions and improving overall device reliability.
Solution Approach 2:
The slit acts as an intermediary element between the first and second channel films. It provides physical separation that prevents the propagation of harmful effects while maintaining the three-dimensional memory structure. The slit bottom shape further mediates electric field distribution to avoid concentration points.
2Productivity
If conventional memory string arrangement is used, then three-dimensional integration is achieved, but performance is limited by lack of structural optimization
Solution Approach 1:
The memory device is segmented into multiple functional regions including first and second channel films, source-side and drain-side regions, and alternating insulating/conductive layers. This segmentation allows independent optimization of each region for enhanced performance while maintaining manufacturability through systematic fabrication processes.
Solution Approach 2:
The patent transitions from conventional two-dimensional memory structures to three-dimensional stacking with vertical channel films and alternating insulating/conductive layers. This dimensional change increases storage density and performance while the systematic layering approach manages the inherent complexity.
3Reliability
If slit is introduced to divide stacks, then reliability is improved by reducing etch damage, but manufacturing complexity increases
Solution Approach 1:
The slit structure and rounded bottom shape are designed and prepared in advance during the fabrication process. By pre-establishing these features before final device operation, the manufacturing process accounts for reliability requirements upfront, simplifying subsequent steps and ensuring consistent results.
Solution Approach 2:
The patent optimizes specific parameters including the slit bottom shape (rounded) and the dimensions of alternating insulating and conductive layers. By carefully controlling these parameters, the device achieves improved reliability through damage reduction while maintaining manufacturing feasibility through standardized process parameters.
4Reliability
If rounded slit bottom is used, then electric field concentration is avoided improving reliability, but manufacturing precision requirements increase
Solution Approach 1:
The slit bottom is designed with a rounded shape instead of a sharp corner. This curvature eliminates electric field concentration points that would occur at sharp angles, improving device reliability. The rounded geometry is achieved through controlled fabrication processes that can produce smooth transitions.
Solution Approach 2:
The patent specifies the rounded bottom shape as a critical geometric parameter. By defining and controlling this parameter during manufacturing, the device achieves reliable electric field distribution. The rounded shape parameter is optimized to balance reliability improvement with manufacturing capability.
Data Source
AI summary
The present disclosure may provide a semiconductor device having a three-dimensional memory device with improved performance and reliability. The device may include a pipe gate having a pipe channel film embedded in the pipe gate. The device may include source-side channel and drain-side channel films coupled respectively to both ends of the pipe channel film. The device may include interlayer insulation films and conductive patterns alternately stacked and disposed over the pipe gate, the alternately stacked interlayer insulation films and conductive patterns surrounding the source-side channel film and the drain-side channel film. The device may include a slit disposed between the drain-side channel film and the source-side channel film and dividing the alternately stacked interlayer insulation films and conductive patterns into a source-side stack and a drain-side stack, the slit having a round shape at a bottom of the slit adjacent to the pipe gate.