3D Memory Slit Structure Layout for Uniform Etching
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in efficiently integrating and etching slit structures within three-dimensional memory devices, leading to non-uniform etching processes and the need for additional process steps to separate memory and pad-out regions.
Innovation Solution
The implementation of a semiconductor device with interleaved conductive and dielectric layers, including a capacitor structure and slit structure, allows for enhanced etching uniformity and reduced duration by increasing the contact area between etchants and sacrificial layers, while retaining dielectric layers for plate line pad-out, thereby improving integration and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If traditional etching processes are used for slit structures in 3D memory devices, then the etching process becomes complex and non-uniform, but the patent implements interleaved conductive and dielectric layers with increased contact area between etchants and sacrificial layers, resulting in enhanced etching uniformity and reduced duration
Solution Approach 1:
The slit structure is divided into multiple segments with interleaved conductive layers (first conductive layers, second conductive layers) and dielectric layers (first dielectric layers, second dielectric layers). This segmentation creates multiple contact areas between etchants and sacrificial layers, enabling uniform etching throughout the 3D structure without requiring complex process steps.
Solution Approach 2:
The patent transitions from traditional 2D etching to 3D multi-layer etching by introducing vertical stacking of conductive and dielectric layers. The etchants can access sacrificial layers from multiple levels simultaneously, transforming the etching process into a three-dimensional operation that achieves uniformity across the entire structure.
2Productivity
If traditional separation methods for memory and pad-out regions are used, then additional process steps are required, but the patent retains dielectric layers for plate line pad-out, simplifying the separation process
Solution Approach 1:
The dielectric layers serve multiple functions: they act as sacrificial layers during etching, provide structural support, and enable plate line pad-out for both memory cells and control circuitries. This multi-functionality eliminates the need for separate pad-out structures, reducing process steps while maintaining integration complexity.
Solution Approach 2:
The dielectric layers are pre-configured with conductive layers interleaved throughout the structure before the final memory formation steps. This preliminary arrangement of conductive and dielectric layers prepares the structure for subsequent etching and pad-out operations, eliminating the need for additional separation process steps.
3Loss of time
If contact area between etchants and sacrificial layers is increased, then etching duration is reduced and uniformity is enhanced, but the structure requires more interleaved layers
Solution Approach 1:
The sacrificial dielectric structure is segmented into multiple discrete layers (first dielectric layers, second dielectric layers) separated by conductive layers. This segmentation creates numerous small contact areas distributed throughout the structure, allowing etchants to simultaneously access multiple sacrificial regions, dramatically reducing total etching time while maintaining uniformity.
Solution Approach 2:
The patent adds vertical dimensionality to the etching process by stacking multiple conductive-dielectric layer pairs. Etchants can penetrate and etch sacrificial layers from multiple vertical levels simultaneously, transforming a sequential single-level etching process into a parallel multi-level operation that reduces overall duration.
Data Source
AI summary
Systems, devices, and methods for managing slit structures in a semiconductor device are provided. In one aspect, a semiconductor device includes a first stack structure having interleaved first conductive layers and first dielectric layers, and a capacitor structure extending through the first stack structure along a first direction. The capacitor structure includes an inner electrode layer, a ferroelectric layer and a plurality of outer electrodes. Adjacent outer electrodes are arranged and isolated from each other along the first direction. The semiconductor device includes a slit structure. A portion of the slit structure extends partially into the first stack structure along a second direction perpendicular to the first direction. The semiconductor device includes a second stack structure adjacent to the first stack structure. The second stack structure includes the first conductive layers interleaved with second dielectric layers.