3D Memory Slot Structure Layout for Self-Aligned Isolation
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Solution Overview
Problem
Conventional vertical memory arrays face challenges in processing conditions for forming aligned contacts as the number of tiers increases, and reducing spacing between vertical memory strings complicates isolation of these structures.
Innovation Solution
The formation of slot structures through self-alignment with pillar structures in a weave pattern, which facilitates increased overlay margin and electrical isolation, is introduced to enhance memory density and reduce processing difficulties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of tiers of conductive structures increases to increase memory density, then memory density is improved, but processing conditions for forming aligned contacts becomes increasingly difficult
Solution Approach 1:
The patent divides the vertical memory array into multiple decks, where each deck contains a subset of the total tiers. This segmentation allows contacts to be formed in a staged manner rather than requiring all contacts to be formed simultaneously, thereby reducing the complexity and improving the precision of contact formation as memory density increases.
Solution Approach 2:
The patent introduces a lateral dimension by forming contacts at different horizontal positions corresponding to different decks. Instead of forming all contacts at a single vertical level, the contact formation process is distributed across multiple vertical levels (decks), transforming a two-dimensional contact formation problem into a three-dimensional staged process that improves alignment precision.
2Quantity of substance
If spacing between adjacent vertical memory strings is reduced to increase memory density, then memory density is improved, but difficulty of isolating vertical memory strings increases
Solution Approach 1:
The patent segments the vertical memory strings into different decks, with each deck containing a portion of the memory strings. This segmentation allows isolation structures to be formed between decks, effectively separating adjacent vertical memory strings even when their spacing is reduced, thereby maintaining ease of manufacture while increasing memory density.
Solution Approach 2:
The patent introduces intermediate isolation structures (such as dielectric materials or sacrificial layers) between adjacent vertical memory strings. These intermediary structures facilitate the isolation process by providing physical and electrical separation, making it easier to manufacture high-density arrays with reduced spacing between memory strings.
3Quantity of substance
If additional tiers of conductive structures are formed to increase memory density, then memory density is improved, but complexity of staircase structures and contact formation increases
Solution Approach 1:
The patent segments the staircase structures into multiple decks, where each deck contains a subset of the total tiers. This segmentation reduces the complexity of individual staircase structures by limiting the number of steps within each deck, making contact formation less complex while still achieving high memory density through the combination of multiple decks.
Solution Approach 2:
The patent resolves staircase structure complexity by distributing tiers across multiple vertical decks rather than concentrating all tiers in a single continuous staircase. This dimensional distribution transforms a complex single-structure problem into simpler multiple-structure problems, each with reduced complexity but collectively achieving the desired memory density.
Data Source
AI summary
A microelectronic device comprises a stack structure comprising alternating conductive structures and insulative structures. Memory cells vertically extend through the stack structure, and comprise a channel material vertically extending through the stack structure. An additional stack structure vertically overlies the stack structure and comprises additional conductive structures and additional insulative structures. First pillar structures extend through the additional stack structure and vertically overlie a portion of the memory cells. Second pillar structures are adjacent to the first pillar structures and extend through the additional stack structure and vertically overlie another portion of the memory cells. Slot structures are laterally adjacent to the first pillar structures and to the second pillar structures and extend through at least a portion of the additional stack structure. A distance between the first pillar structures and the slot structures is substantially equal to a distance between the second pillar structures and the slot structures.