Memory Sub-System Slow Block Detection in Multi-Plane Programming
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Solution Overview
Problem
Existing memory sub-systems face issues with slow program rates leading to unnecessary discarding of good blocks due to simultaneous multi-plane programming, causing errors and inefficiencies.
Innovation Solution
Implementing a memory sub-system that monitors and determines program pulse counts to detect slow programming, shifting from multi-plane to single-plane programming based on threshold pulse counts to prevent errors and maintain usable blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If simultaneous multi-plane programming is used, then programming speed is improved, but good blocks are incorrectly discarded due to slow program rates in individual blocks
Solution Approach 1:
The patent segments the programming process by monitoring program pulse counts for individual blocks within planes during simultaneous multi-plane programming. By dividing the monitoring task into block-level segments, the system can identify slow program blocks without sacrificing the overall programming speed benefits of multi-plane operation.
Solution Approach 2:
The patent implements feedback mechanisms by continuously monitoring program pulse counts during the programming process. This feedback allows the system to detect when individual blocks are programming slowly and trigger appropriate responses, such as switching to single-plane programming for affected blocks, thereby maintaining reliable block identification.
2Measurement precision
If program pulse count monitoring is implemented, then slow block detection accuracy is improved, but system complexity increases
Solution Approach 1:
The patent employs self-service by utilizing existing programming infrastructure to perform monitoring functions. The same hardware that programs blocks also counts program pulses, eliminating the need for separate dedicated monitoring hardware and reducing overall system complexity while maintaining detection accuracy.
Solution Approach 2:
The patent merges the programming and monitoring functions into a unified process. By combining these operations, the system achieves accurate slow block detection without requiring separate complex monitoring subsystems, thus improving measurement precision while controlling device complexity.
3Reliability
If single-plane programming is used for slow blocks, then programming errors are prevented, but overall programming productivity decreases
Solution Approach 1:
The patent applies local quality by treating slow program blocks differently from normal blocks. Instead of switching all planes to single-plane programming, the system applies single-plane programming only to identified slow blocks while maintaining multi-plane programming for other blocks, thus preventing errors in problematic areas without sacrificing overall productivity.
Solution Approach 2:
The patent uses partial action by applying single-plane programming selectively only to the extent necessary for slow blocks rather than universally. This partial application of the slower programming method prevents programming errors in affected blocks while minimizing the impact on overall programming throughput.
Data Source
AI summary
An example apparatus can include a program component. The program component can program each of a plurality of planes during different time periods subsequent to performing a multi-plane programming on a non-volatile memory array. The program component can monitor a program pulse count for each of the respective plurality of planes per super block. The program component can, in response to the program pulse count for a respective block within one of the plurality of planes being above a threshold pulse count, determine that the respective block is a bad block.