Memory-Interface SoC Training to Compensate VT Variation Delays
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Solution Overview
Problem
Existing memory controllers or system-on-chips (SoCs) face performance deterioration during data training on memory devices due to limited access and internal characteristics of the memory devices, particularly due to VT variation, which prolongs the training time.
Innovation Solution
The SoC includes a control logic circuit that sequentially transmits pieces of data with different delay times based on a pre-stored edge code, continuously transmits read commands to read stored data, and determines a delay value based on the data pattern of reception data, thereby minimizing training time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data training is performed on the memory device to compensate for delay due to VT variation, then the reliability of data transmission is improved, but the time required for training increases and access to the memory device is limited
Solution Approach 1:
The patent applies preliminary action by performing data training before normal data transmission operations. The control logic circuit executes training sequences that write test data to the memory device, read it back, and analyze timing characteristics to determine optimal delay compensation values. This preliminary training ensures that subsequent data transmissions operate at peak reliability without requiring real-time adjustments during normal operation.
Solution Approach 2:
The patent implements dynamics by making the delay compensation value adjustable based on training results. The control logic circuit dynamically determines the optimal delay value through training and then applies this value to synchronize data transmission timing. This dynamic adjustment allows the system to adapt to VT variations while minimizing training time through intelligent algorithms that converge on optimal parameters efficiently.
2Measurement precision
If data training is performed on the memory device to compensate for delay due to VT variation, then the data transmission accuracy is improved, but the performance of the memory system deteriorates during training
Solution Approach 1:
The training operation is performed as a preliminary action before normal memory operations begin. The control logic circuit executes a complete training sequence including writing training data, reading it back, analyzing timing delays, and determining optimal compensation values. Once training is complete, the system transitions to high-performance normal operation mode, ensuring that productivity losses are confined to the initial training phase rather than affecting ongoing operations.
Solution Approach 2:
The patent employs skipping by using optimized training algorithms that rapidly converge on optimal delay compensation values. Rather than exhaustively testing all possible timing parameters, the control logic circuit uses intelligent search methods to quickly identify effective delay values, thereby rushing through the training process as efficiently as possible while still achieving the required measurement precision for accurate data transmission.
Data Source
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AI summary
Disclosed is a SoC. The SoC for communicating with a memory device includes a memory interface that exchanges a command and data with the memory device, and a control logic circuit that transmits a clock signal and a plurality of data signals to the memory device through the memory interface. The control logic circuit sequentially transmits pieces of first data with different delay times to the memory device through the memory interface based on a pre-stored first edge code, continuously transmits, to the memory device, a plurality of read commands for reading the pieces of first data stored in the memory device from the memory device, and obtains a first delay value including an extent, to which the pieces of first data are delayed, based on a data pattern of each of pieces of first reception data read from the memory device in response to the plurality of read commands.