Memory Soft Decoding with Multi-Latch Page Transfer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems face inefficiencies in soft decoding processes due to cache size limitations, requiring multiple read operations to recover data, which increases time and power consumption.
Innovation Solution
Implementing a soft data multiple bit read protocol that allows for storing and transferring data in a memory device using three latches, enabling efficient soft decoding by reducing the number of read commands needed, thus optimizing cache utilization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple read operations are performed to recover data due to cache size limitations, then data recovery is achieved, but time consumption increases
Solution Approach 1:
The patent segments data into soft data and hard data components, storing them in separate latches within the memory device. This segmentation allows the memory device to prepare multiple data types simultaneously, enabling the memory controller to perform soft decoding operations more efficiently by having all necessary data components readily available, thus reducing the number of sequential read operations required and lowering time consumption.
2Reliability
If multiple read operations are performed to recover data due to cache size limitations, then data recovery is achieved, but power consumption increases
Solution Approach 1:
The patent segments data into soft data and hard data components, storing them in separate latches within the memory device. This segmentation allows the memory device to prepare multiple data types simultaneously, enabling the memory controller to perform soft decoding operations more efficiently by having all necessary data components readily available, thus reducing the number of sequential read operations required and lowering power consumption.
Solution Approach 2:
The patent implements preliminary action by having the memory device store soft data, inverted soft data, and hard data in separate latches in advance, before the memory controller needs to perform soft decoding. This preliminary preparation ensures that all required data is already positioned and ready for immediate use, eliminating the need for multiple sequential read operations and thereby reducing both time and power consumption during the actual decoding process.
3Productivity
If cache size is increased to reduce read operations, then read efficiency improves, but device complexity increases
Solution Approach 1:
The patent segments data into soft data and hard data components, storing them in separate latches within the memory device. This segmentation allows the memory device to prepare multiple data types simultaneously, enabling the memory controller to perform soft decoding operations more efficiently by having all necessary data components readily available, thus reducing the number of sequential read operations required and lowering time consumption.
Solution Approach 2:
The patent resolves the cache size dilemma by shifting the solution from increasing cache dimension (size) to adding functional dimension (separate latches for different data types). Instead of enlarging the cache, the invention introduces multiple specialized latches within the memory device that can hold soft data, inverted soft data, and hard data simultaneously, enabling efficient soft decoding without increasing overall memory capacity or device complexity.
Data Source
AI summary
The present disclosure involves methods, apparatuses, and systems for performing soft decoding in a memory system. In one example, a method for a memory system includes sending, by a memory controller, a read command to a memory device. The method further includes storing, by the memory device based on the read command, first soft data in a first latch, second soft data in a second latch, and hard data in a third latch. The method further includes sending, by the memory controller, a first page transfer command to the memory device, wherein the first page transfer command indicates a selected latch from the first latch, the second latch, or the third latch to transfer data in the selected latch to a cache latch.