Memory Controller Soft Decoding for Faster Product Code Correction
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Solution Overview
Problem
Existing memory controllers face challenges in achieving high error correction capabilities while maintaining efficient processing times, particularly in decoding methods for product codes used in storage devices, where SISO decoding requires longer processing times and HIHO decoding has limited error correction capacity.
Innovation Solution
A memory controller with a soft decision decoder that uses two tables to calculate and output extrinsic values based on distance information and decoding success rates, iteratively improving error correction by exchanging extrinsic values between decoding processes of different dimensional codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SISO decoding is used to improve error correction capability, then decoding success rate is improved, but processing time increases
Solution Approach 1:
The patent segments the decoding process into two distinct decoders: a first decoder for first-dimensional codes and a second decoder for second-dimensional codes. Each decoder operates independently on its respective dimension, allowing parallel processing and reducing overall processing time while maintaining the error correction benefits of SISO decoding through iterative exchange of extrinsic values between the two decoders.
Solution Approach 2:
The patent implements a limited number of iteration steps between the two decoders rather than exhaustive iterations. This partial action approach achieves sufficient error correction capability without the excessive processing time that would result from multiple full SISO decoding iterations, thus resolving the contradiction between reliability and time loss.
2Productivity
If HIHO decoding is used to reduce processing time, then processing efficiency is improved, but error correction capacity is limited
Solution Approach 1:
By dividing the decoding task into two separate decoders handling different dimensions, the system achieves HIHO-like processing efficiency in each dimension while the combined iterative operation provides enhanced error correction capacity beyond what a single HIHO decoder could achieve alone.
Solution Approach 2:
The patent creates a composite decoding system that combines two different decoding approaches (first decoder and second decoder operating on different dimensions) to achieve properties that neither component alone could provide: both processing efficiency and enhanced error correction capacity.
3Measurement precision
If iterative decoding with multiple steps is used to improve decoding accuracy, then decoding success rate is improved, but device complexity increases
Solution Approach 1:
The patent segments the complex iterative decoding process into two simpler, specialized decoders that each handle one dimension. This segmentation reduces the complexity of individual decoder units while achieving high decoding accuracy through their coordinated iterative operation, thus resolving the contradiction between precision and device complexity.
Data Source
AI summary
A memory controller according to an embodiment includes a first decoder which calculates first extrinsic value based on a decoding success rate specified using a first table showing a correspondence between first distance information indicating a square Euclidean distance between a first decode word and a first soft input value and a first decoding success rate indicating a probability of a decoding result that the first decode word is correct, and a second decoder which calculates second extrinsic value based on a decoding success rate specified using the second table showing a correspondence second distance information indicating a square Euclidean distance between a second decode word and a second soft input value and a second decoding success rate indicating a probability of a decoding result that the second decode word is correct.