Memory Cell Soft Erase for Upper-Tail Threshold Tightening
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Solution Overview
Problem
Existing memory devices face challenges in maintaining a sufficient read window budget (RWB) due to widening threshold voltage distributions, particularly at the upper tail, which occurs from quick and long-term charge loss, leading to difficulty in accurately measuring separate distributions and impacting programming efficiency.
Innovation Solution
Implementing a fast bit erase or soft erase method on individual memory cells to partially erase the threshold voltage, specifically targeting the upper tail, by controlling the application of voltages to pillars and wordlines, allowing for incremental tightening of the threshold voltage distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If fast bit erase is applied to tighten upper tail, then threshold voltage distribution precision is improved, but device complexity increases
Solution Approach 1:
The patent segments the erase operation into selective bit-level erasure rather than full block erasure. By targeting only specific memory cells with threshold voltages above a verify voltage threshold, the method divides the erase operation into manageable segments, improving precision while controlling complexity through selective application.
Solution Approach 2:
The patent applies different voltage conditions to different memory cells based on their individual threshold voltage states. Cells exceeding the verify voltage threshold receive the fast bit erase operation, while others remain unaffected. This local differentiation tightens the upper tail of the threshold voltage distribution without unnecessarily processing all cells.
2Manufacturing precision
If fast bit erase is applied to tighten upper tail, then programming accuracy is improved, but operation time increases
Solution Approach 1:
The patent performs partial erasure by applying the fast bit erase operation only to memory cells that exceed the verify voltage threshold. This partial action is sufficient to tighten the upper tail of the threshold voltage distribution and improve programming accuracy, while avoiding the time cost of processing all memory cells in the block.
Solution Approach 2:
The method incorporates a verify voltage threshold as a feedback mechanism. Memory cells are evaluated against this threshold, and only those exceeding it undergo fast bit erase. This feedback-based selection ensures that erasure operations are applied only when and where needed, balancing accuracy improvement with time efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method effectively mitigates upper tail over-programming, improves RWB, enhances programming accuracy, and improves endurance by narrowing the threshold voltage distributions, especially in multi-level cells.
Implementation Method 1
causing a voltage of the second pillar to float
Implementation Method 2
causing a soft erase voltage between a channel of the memory cell and the selected wordline
Data Source
AI summary
A memory device includes a first pillar coupled with a first data line, a second pillar coupled with a second data line, and wordlines coupled with first and second pillars. Control logic may cause wordlines to be discharged after a program pulse is applied to selected wordline. The control logic may apply a supply voltage to second data line to cause a voltage of second pillar to float. The control logic may apply a ground voltage to the first data line to inhibit soft erase associated with the selected wordline via first pillar.