Memory Page Soft Reads for Selective Background Refresh
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Solution Overview
Problem
Existing memory systems face inefficiencies in managing bit errors, leading to increased I/O bandwidth and power consumption due to periodic refreshes, which can degrade memory performance and QoS latency.
Innovation Solution
Implementing a method to monitor page validity conditions and adaptively control error correction or background data refresh by identifying pages with high bit error counts and selectively refreshing them without using ECC, counting bits in a valley susceptible to errors, thereby reducing I/O power consumption and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic refreshes are performed to mitigate bit error accumulation, then data reliability is improved, but I/O bandwidth and power consumption increase
Solution Approach 1:
The system performs preliminary actions by reading memory pages in advance during idle periods to assess error conditions before they affect data integrity. This allows the system to proactively identify pages needing refresh without waiting for errors to accumulate to critical levels, thereby reducing the frequency and intensity of I/O operations required for maintenance.
Solution Approach 2:
The system implements feedback mechanisms by continuously monitoring bit error counts and valley bit metrics from memory pages. Based on this feedback, the system dynamically adjusts refresh strategies, refreshing only pages with high error counts rather than uniformly refreshing all pages, thus optimizing power consumption while maintaining reliability.
2Reliability
If periodic refreshes are performed to mitigate bit error accumulation, then data reliability is improved, but I/O bandwidth is consumed
Solution Approach 1:
The system applies local quality by treating different memory pages differently based on their individual error characteristics. Instead of uniform refresh of all pages, the system identifies and refreshes only specific pages with high bit error counts, leaving pages with low error counts unchanged. This localized approach preserves I/O bandwidth for host operations while maintaining reliability where needed.
Solution Approach 2:
The system performs preliminary assessment of memory page health by reading valley bits and counting errors during low-priority periods. This preliminary action allows the system to plan refresh operations efficiently, avoiding unnecessary I/O bandwidth consumption by only initiating refreshes for pages that truly require them, thus preserving bandwidth for productive host operations.
3Reliability
If ECC is used to correct errors, then data reliability is improved, but device complexity increases
Solution Approach 1:
The system extracts the error monitoring function from the traditional ECC framework. Instead of using complex ECC codes that require decoding operations, the system separately extracts and monitors specific error indicators (valley bits) to assess page health. This extraction approach simplifies the overall system by avoiding the complexity of full ECC implementation while maintaining the ability to detect and respond to errors.
Solution Approach 2:
The system uses feedback from simplified valley bit counting to drive refresh decisions, replacing the need for complex ECC decoding. The feedback mechanism directly monitors error conditions and triggers appropriate responses (refresh or ignore) without requiring the complex computational overhead of traditional ECC, thus maintaining reliability while reducing device complexity.
Data Source
AI summary
This application is directed to data validation and refresh in an electronic device having a memory device. The memory device receives an inquiry for a validity condition of a page of the memory device, which includes a plurality of memory cells that store two consecutive data items and correspond to two nominal threshold voltages. In response to the inquiry, the memory device selects a first readout voltage and a second readout voltage between the two nominal threshold voltages, and applies the first readout voltage and the second readout voltage to read the plurality of memory cells and generate first readout data and second readout data, respectively. An error rate of the page is determined based on the first readout data and the second readout data, and in some embodiments, further used to determine whether an error correction process or a background data refresh need to be implemented on the page.