Vertical Memory Source Formation via Cavity Etching
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Solution Overview
Problem
The increasing aspect ratios of memory cell pillars in semiconductor devices lead to alignment issues during the pillar punch etch process, making it challenging to electrically connect channel regions to the source in vertical memory arrays, which affects the integration density and performance of memory devices.
Innovation Solution
A semiconductor device design where the source is positioned below the memory cells and surrounded by cell films, eliminating the need for a pillar punch etch process, and access is provided through large tier openings or contact openings, allowing for simultaneous dopant activation and metallization of the source and drain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pillar punch etch process is used to electrically connect channel regions to source, then memory device can be manufactured, but alignment issues occur as aspect ratios of memory cell pillars increase
Solution Approach 1:
The patent removes the pillar punch etch process entirely from the manufacturing sequence. Instead of using this problematic etching step to create electrical connections, the invention forms the source region directly in electrical contact with channel regions through a different fabrication approach that avoids the alignment issues associated with high aspect ratio pillars
Solution Approach 2:
The source region is formed in advance during the fabrication process before final device assembly, positioned directly adjacent to channel regions. This preliminary formation of the source ensures inherent electrical connection without requiring subsequent alignment-critical etching steps
2Productivity
If memory cell pillar dimensions are reduced to increase integration density, then more memory cells fit in unit area, but alignment issues during pillar punch etch become more severe
Solution Approach 1:
The patent eliminates the pillar punch etch process that causes alignment problems when scaling to higher densities. By removing this process step entirely, the invention enables continued reduction of memory cell pillar dimensions without the compounding alignment difficulties that would otherwise occur
Solution Approach 2:
The invention transitions from a vertical pillar-based connection approach to a lateral source region formation approach. Instead of etching vertically through high aspect ratio pillars, the source is formed in a lateral configuration that achieves electrical connection without requiring precise vertical alignment through the pillar structure
Data Source
AI summary
A method of forming a semiconductor device comprises forming sacrificial structures and support pillars on a material. Tiers are formed over the sacrificial structures and support pillars and tier pillars and tier openings are formed to expose the sacrificial structures. One or more of the tier openings comprises a greater critical dimension than the other tier openings. The sacrificial structures are removed to form a cavity. A cell film is formed over sidewalls of the tier pillars, the cavity, and the one or more tier openings. A fill material is formed in the tier openings and adjacent to the cell film and a portion removed from the other tier openings to form recesses adjacent to an uppermost tier. Substantially all of the fill material is removed from the one or more tier openings. A doped polysilicon material is formed in the recesses and the one or more tier openings. A conductive material is formed in the recesses and in the one or more tier openings. An opening is formed in a slit region and a dielectric material is formed in the opening. Additional methods, semiconductor devices, and systems are disclosed.