Memory Programming via Source-Side Injection and Charge Trapping
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Solution Overview
Problem
As memory devices are miniaturized, punch-through current between cells increases, degrading the stability and performance of non-volatile memory cells during programming operations due to unselected cells' influence.
Innovation Solution
A method where a first cell is programmed by source-side injection and channel-hot-carrier injection, with a neighboring cell acting as a switching transistor, applying specific voltages to control gates and source/drain regions to manage carrier flow into a charge storage layer, and using voltage pulses to control channel states for efficient data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory device dimensions are reduced to increase integration, then device integration is improved, but punch-through current between cells increases degrading programming stability
Solution Approach 1:
A charge trapping layer is introduced as an intermediary between the floating gate and the substrate. This charge trapping layer captures and isolates punch-through current carriers generated by unselected cells, preventing them from reaching the floating gate and interfering with the programming operation of selected cells. The intermediary layer thus decouples the harmful effect of miniaturization from the programming stability.
2Ease of manufacture
If conventional programming methods are used in miniaturized devices, then manufacturing simplicity is maintained, but programming speed decreases due to punch-through current interference
Solution Approach 1:
The patent modifies the electrical parameters during programming by applying specific voltage sequences to control gates and bit lines. The method uses parameter changes including: (1) applying a first voltage to the control gate of the selected cell, (2) applying a second voltage to the control gate of the unselected cell to keep its channel off, and (3) applying third and fourth voltages to bit lines to generate carriers that flow through the selected cell. These controlled parameter changes enable fast programming by source-side injection while maintaining manufacturing simplicity.
3Ease of operation
If unselected cells are left active during programming, then device operation simplicity is maintained, but programming window narrows due to carrier injection interference
Solution Approach 1:
The patent dynamically controls the state of unselected cells during programming by applying a second voltage to their control gates. This voltage is specifically designed to keep the channel of unselected cells turned off, dynamically preventing them from generating harmful punch-through current. The dynamic control allows the memory device to maintain ease of operation while significantly widening the programming window by eliminating interference from unselected cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances programming speed, increases device integration, and widens the memory programming window, allowing for multi-bit data storage in a single memory cell set while inhibiting unselected cells from being programmed.
Implementation Method 1
A charge trapping layer is disposed between the floating gate and the substrate. The charge trapping layer is capable of trapping carriers provided by punch-through current
Implementation Method 2
hot carriers are generated and injected into a charge storage layer through a floating gate
Implementation Method 3
the carriers are injected into a charge storage layer of the first cell by the source-side injection
Data Source
AI summary
A method of programming a memory is provided. The memory has a first cell, having a first S/D region and a second S/D region shared with a second cell. The second cell has a third S/D region opposite to the second S/D region. When programming the first cell, a first voltage is applied to a control gate of the first cell, a second voltage is applied to a control gate of the second cell to slightly turn on a channel of the second cell, a third and a fourth voltage are respectively applied to the first and the third S/D regions, and the second S/D region is floating. A carrier flows from the third S/D region to the first S/D region, and is injected into a charge storage layer of the first cell by source-side injection.