Memory Device Source Line Byte Selection Area Reduction
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Solution Overview
Problem
Conventional memory devices require byte select transistors that occupy a significant area of the chip, limiting the density of data storage and efficiency in high-density memory applications.
Innovation Solution
The use of separate source lines to select memory bytes for functions like byte erase and write, eliminating the need for byte select transistors and thereby reducing device area, with each memory section sharing a common source line and using a select transistor and a sense transistor for memory cell selection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If byte select transistors are used to control memory sections, then memory cell selection is reliable, but device area increases significantly
Solution Approach 1:
The patent removes the byte select transistor from the memory cell structure entirely. Instead of using a byte select transistor to control memory sections, the invention uses the source line voltage to directly control the selection of memory bytes. This extraction of the byte select transistor eliminates the area overhead while maintaining selection functionality through the modified source line control mechanism.
Solution Approach 2:
The source line is given multiple functions: it serves as both the source connection for the memory cell transistors and the control line for selecting memory bytes. By applying different voltages to the source line, the system can control which memory bytes are selected for operations without requiring dedicated byte select transistors. This multi-functionality consolidates the control mechanism and reduces device area.
2Productivity
If separate source lines are used for each memory section, then memory byte selection efficiency improves, but device area increases
Solution Approach 1:
The patent merges the source lines for multiple memory sections into a single shared source line. Instead of providing separate source lines for each memory section (which would increase area), the invention uses one source line that serves multiple memory sections. The voltage applied to this shared source line controls the selection of specific memory bytes across the different sections, achieving efficient selection without the area penalty of separate source lines.
Data Source
AI summary
A memory device comprises memory cells arranged in rows and columns, and source lines associated with memory sections, each of which includes a plurality of memory cells. Source terminals of transistors included in the memory cells in a first memory section are physically coupled to a first source line that is distinct from other source lines associated with other memory sections on a same row of the memory device as the first memory section. Gate terminals of transistors included in memory cells in a row share a common wordline configured for providing a signal to the gate terminals.