Nonvolatile Memory Source Line Potential Detection Circuit
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Solution Overview
Problem
As nonvolatile semiconductor memory capacities increase, programming large page sizes require high peak currents, leading to noise, malfunctions, and reduced reliability due to low power supply potentials, and result in high power consumption, necessitating a reduction in power consumption to improve memory system performance.
Innovation Solution
The implementation of a nonvolatile semiconductor memory design that separates the programming of odd-numbered and even-numbered bit lines, using a cell-source driver to set the source line on a fixed potential, a data latch circuit to temporarily store program data, a hookup circuit to connect bit lines to the source line, and a level detection circuit to determine the completion of bit line charging based on the source line potential, allowing for variable charge times and reduced peak currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If programming is performed for each page with increasing memory capacity, then memory capacity increases, but peak current increases causing noise and reliability issues
Solution Approach 1:
The bit line charging operation is divided into two separate phases: odd-numbered bit lines are charged in a first period, and even-numbered bit lines are charged in a second period. This segmentation of the charging process reduces the simultaneous current demand, thereby suppressing peak current while maintaining the ability to program large page sizes with increased memory capacity.
2Quantity of substance
If programming is performed for each page with increasing memory capacity, then memory capacity increases, but power consumption increases
Solution Approach 1:
The charging of bit lines is segmented into two distinct time periods: odd-numbered bit lines are charged during a first period, and even-numbered bit lines are charged during a second period. This temporal segmentation reduces the peak power consumption by preventing simultaneous charging of all bit lines, thereby addressing the power consumption issue while maintaining support for large memory capacities.
3Object-generated harmful factors
If charge time of bit lines is extended to reduce peak current, then peak current is suppressed, but programming time increases
Solution Approach 1:
The bit line charging process is segmented into two parallel phases: odd-numbered bit lines are charged in a first period while even-numbered bit lines wait, then even-numbered bit lines are charged in a second period while odd-numbered bit lines complete their charging. This segmented approach suppresses peak current by avoiding simultaneous charging, yet maintains efficient programming time by overlapping the charging phases rather than sequentially charging all bit lines one after another.
4Productivity
If simultaneous charging of all bit lines is performed, then programming speed is maintained, but peak current causes malfunction due to low power supply potential
Solution Approach 1:
The simultaneous charging of all bit lines is divided into two sequential phases: odd-numbered bit lines are charged in a first period, and even-numbered bit lines are charged in a second period. This segmentation eliminates the peak current surge that causes malfunction due to low power supply potential, while maintaining programming speed efficiency by charging bit lines in overlapping parallel phases rather than strict sequential order.
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory includes a source line connected to first and second cell units, a cell-source driver setting the source line on a fixed potential in a programming, a data latch circuit temporary storing program data, a hookup circuit connecting one of the first and second bit lines to the data latch circuit, and connecting the other one of the first and second bit lines to the source line, in the programming, a level detection circuit detecting a potential level of the source line, and a control circuit determining a completion of a charge of the first and second bit lines when the potential level of the source line is larger than a threshold value, and making a charge time of the first and second bit lines variable, in the programming.