3D Memory Source-Line Layout With Dummy Bit Lines
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Solution Overview
Problem
Existing memory devices face challenges in reducing the resistance of the path through which a source voltage is transmitted, limiting the efficiency and performance of the memory device.
Innovation Solution
The memory device incorporates a 3D structure with widened regions of dummy bit lines to transfer the source voltage, utilizing a double spacer patterning method to enhance the layout and manufacturing process, thereby reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the resistance of the source voltage transmission path is reduced, then the efficiency and performance of the memory device is improved, but the structural complexity and manufacturing difficulty increase
Solution Approach 1:
The patent introduces dummy bit lines in the third dimension (vertical stacking) between normal bit lines to create additional voltage transmission paths. This 3D arrangement allows voltage to be delivered to memory blocks more efficiently without increasing planar complexity, as the dummy bit lines are positioned above existing bit lines rather than expanding the 2D layout.
Solution Approach 2:
The patent creates dummy bit lines that are copies of normal bit lines but without memory cells. These dummy bit lines replicate the structural and electrical characteristics of functional bit lines, allowing them to serve as voltage transmission pathways while consuming no additional planar space, thus reducing overall resistance without proportionally increasing device complexity.
2Reliability
If dummy bit lines are added to reduce resistance, then the source voltage transmission path is improved, but the manufacturing process complexity increases
Solution Approach 1:
The patent employs preliminary spacer formation steps where spacers are deposited and patterned before final bit line formation. The first and second spacers are created in sequence, with the first spacers serving as templates for the second spacers. This staged approach breaks down the complex task of creating precisely positioned dummy bit lines into manageable steps, improving manufacturability despite the additional process steps.
Solution Approach 2:
The spacers act as intermediary structures that mediate between the patterning process and the final dummy bit line formation. The spacers are formed through deposition and etching processes, serving as temporary templates that define the precise locations of dummy bit lines. This intermediary approach enables precise positioning of dummy bit lines without requiring direct complex patterning, thereby facilitating manufacturing.
Data Source
AI summary
Provided herein may be a memory device and a method of manufacturing the same. The memory device may include a plurality of memory blocks formed on a source line, the plurality of memory blocks separated by a slit, a source contact formed in the slit, a plurality of normal bit lines arranged, in parallel, over the memory blocks, the plurality of normal bit lines being spaced apart in a first direction and extending in a second direction, a plurality of dummy groups disposed between the plurality of normal bit lines, each of the plurality of dummy groups including dummy bit lines, a first dummy pad extending in the first direction and contacting end portions of the dummy groups, a first upper contact formed on the first dummy pad, and a lower contact formed between the dummy bit lines and the source contact.