3D Memory Cell Array Common Source Line for Leakage Control
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Solution Overview
Problem
Existing integrated circuit memory devices face challenges in increasing data storage capacity while maintaining operational reliability, particularly in systems requiring high-capacity data storage.
Innovation Solution
The integration of a vertically-stacked memory cell array structure with a common source line and gate stack, featuring monocrystalline channel layers and semiconductor layers, enhances data storage capacity and operational reliability by preventing metal silicide diffusion through the use of cover layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vertically-stacked memory cell array structure is integrated to increase data storage capacity, then storage capacity is improved, but metal silicide diffusion occurs which deteriorates operational reliability
Solution Approach 1:
A cover layer is introduced as an intermediary barrier between the semiconductor layer and the channel layer. This cover layer prevents metal silicide diffusion from the semiconductor layer into the channel layer, thereby maintaining operational reliability while allowing the vertically-stacked structure to achieve high storage capacity.
Solution Approach 2:
The structure employs a composite multi-layer configuration consisting of the common source line, semiconductor layer, cover layer, and channel layer. Each layer is composed of specific materials with distinct properties that work together to achieve both high storage capacity and operational reliability by preventing harmful diffusion while maintaining electrical functionality.
2Quantity of substance
If vertically-stacked memory cell array structure is integrated to increase data storage capacity, then storage capacity is improved, but leakage currents increase which deteriorates operational reliability
Solution Approach 1:
The cover layer serves as an intermediary barrier that prevents direct contact between the semiconductor layer and channel layer, thereby blocking leakage current paths. This allows the vertically-stacked structure to achieve high storage capacity while maintaining low leakage currents and operational reliability.
3Quantity of substance
If vertically-stacked memory cell array structure is integrated to increase data storage capacity, then storage capacity is improved, but structural integrity is compromised
Solution Approach 1:
The multi-layer composite structure comprising the common source line, semiconductor layer, cover layer, and channel layer provides enhanced structural integrity. Each layer is carefully engineered with specific materials and thicknesses to maintain mechanical stability and prevent degradation while enabling the vertically-stacked configuration for high storage capacity.
Data Source
AI summary
An integrated circuit device includes a substrate having a peripheral circuit structure thereon, and a cell array structure extending on the peripheral circuit structure. The cell array structure includes: a gate stack including a plurality of insulation layers and a plurality of gate lines alternately arranged on the substrate, a plurality of channel structures each penetrating through the gate stack in a vertical direction perpendicular to a top surface of the substrate and comprising a monocrystalline channel layer, and a common source line, which extends on the gate stack, is in contact with the channel layer of the channel structure, and includes a semiconductor layer and a cover layer provided between the semiconductor layer and the channel layer.