Nonvolatile Memory Common Source Line Segmentation for Read Disturbance
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Solution Overview
Problem
Nonvolatile memory devices face bit errors due to read disturbances, which can lead to increased read cycles and wear on memory cells, and may result in read failures and the need for block replacement, especially when repeatedly reading specific pages.
Innovation Solution
A nonvolatile memory device with a memory cell array and control logic circuit that independently controls common source lines, applying ground voltage to one and a predetermined voltage to the other during read operations, thereby reducing noise and preventing soft-programming of memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a read operation is performed on a selected memory cell, then data is read from the memory cell, but read disturbances occur causing bit errors in adjacent memory cells
Solution Approach 1:
The patent divides the common source line into multiple independently controllable segments (first common source line and second common source line). During a read operation, different voltage levels can be applied to different segments, allowing the selected cell's source line to be at ground voltage while adjacent cells' source lines are at a higher voltage, thus preventing read disturbances in adjacent cells while maintaining data accuracy in the selected cell.
Solution Approach 2:
The patent applies different voltage conditions to different regions of the memory array during read operations. The selected memory cell's common source line is set to ground voltage for accurate reading, while adjacent memory cells' common source lines are set to a predetermined voltage level to prevent unwanted charge transfer and read disturbances, thereby achieving local optimization of read safety.
2Productivity
If repeated read operations are performed on specific pages, then data access is maintained, but memory cell wear increases and block replacement may be needed
Solution Approach 1:
By segmenting the common source line control into multiple independently controllable lines, the patent enables selective voltage application during repeated read operations. This reduces the cumulative wear on memory cells by preventing charge transfer disturbances during each read cycle, thereby extending the operational lifespan of memory blocks while maintaining fast read access performance.
Solution Approach 2:
The patent applies a predetermined voltage to the common source lines of adjacent memory cells before the read operation completes, as a preventive measure against read disturbances. This preliminary protective action prevents charge transfer to adjacent cells during repeated reads, reducing wear accumulation and extending memory block lifespan without impacting read speed.
3Reliability
If independent control of common source lines is implemented, then read disturbances are reduced, but device complexity increases
Solution Approach 1:
The patent segments the common source line into multiple independently controllable parts (first and second common source lines). While this increases control complexity, the segmentation enables precise voltage control during read operations, reducing read disturbances and improving read safety. The increased complexity is traded for significantly improved reliability in preventing bit errors.
Data Source
AI summary
Disclosed is a nonvolatile memory including a memory cell array including a first cell string connected between a first bit line and a first common source line, and a second cell string a second common source line and a second bit line adjacent to the first bit line. The nonvolatile memory also includes a control logic circuit configured to independently control the first and second common source lines.