Memory Device Source-Line Segmentation for Read-Margin Protection

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Solution Overview

Problem

Existing memory devices face challenges in efficiently managing the current discharge during read operations due to the need for large source line drivers when multiple memory cells are read simultaneously, leading to potential damage and reduced read margins.

Innovation Solution

The implementation of a memory device architecture that couples source lines to subsets of memory cells, utilizing separate source line drivers for each subset, allowing for reduced driver size and improved current discharge rates during read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If a single source line driver is used to read multiple memory cells simultaneously, then the read operation can access more data in parallel, but the driver size must be large enough to handle the total current from all selected cells, which can cause damage and reduce read margins

Engineering Contradiction:
Improveread parallelismVSAvoidread margin
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent divides the memory array into multiple blocks, where each block is associated with a separate source line driver. During read operations, only the source line drivers corresponding to actively read blocks are enabled, limiting current discharge to a subset of memory cells rather than all selected cells across the entire array. This segmentation prevents any single driver from being overloaded while maintaining parallel read capability across multiple blocks.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If the source line driver is designed to handle current from all memory cells, then any cell can be read, but the driver size increases and may cause damage during simultaneous reads

Engineering Contradiction:
Improveread coverageVSAvoiddriver size
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The memory array is segmented into multiple blocks with dedicated source line drivers for each block. This allows the system to maintain adaptability by enabling reads from any block independently, while each individual driver remains compact since it only needs to handle current from its specific block rather than the entire array.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The system dynamically enables or disables specific source line drivers based on which blocks contain the data being read. This dynamic activation allows the memory device to adapt to different read patterns and access only the necessary drivers, maintaining versatility while avoiding the need for all drivers to be permanently sized for maximum load.

Inventive Principle:
Principle #15Dynamics

3Reliability

If multiple source line drivers are used for different subsets of memory cells, then current discharge is limited to selected cells improving read margin, but the overall device complexity increases

Engineering Contradiction:
Improveread marginVSAvoidnumber of drivers
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The memory array is divided into multiple blocks, each with its own source line driver. This segmentation improves read margin by limiting current discharge to cells within active blocks only, while the number of drivers is optimized by having one driver per block rather than one per row or column, balancing reliability improvement with manageable device complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS20250322879A1Memory device and method of operation
Publication Date: 2025.10.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20250322879A1 patent drawing
  • US20250322879A1 patent drawing
  • US20250322879A1 patent drawing

AI summary

A memory device includes a column of at least three memory cells and a source line coupled to the source terminal of each memory cell. A source line driver is coupled to the source line, a voltage terminal, and a program voltage source and is switchable between a program operation, an erase operation, and a read operation.