3D Memory Source-Line Switching for Lower Voltage Drop
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Solution Overview
Problem
The integration limit of semiconductor devices is reached when forming memory cells in a single layer on a substrate, necessitating a three-dimensional stacking approach to enhance operational reliability and efficiency.
Innovation Solution
A semiconductor device with stacked memory cells and controlled source voltage application through local source lines and pass transistors, allowing selective voltage application to memory blocks or sub-memory blocks, reducing source capacitance and current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If memory cells are formed in a single layer on a substrate, then the manufacturing process is simple, but the integration degree reaches a limit and cannot be improved further
Solution Approach 1:
The patent transitions from two-dimensional planar memory cell arrangement to three-dimensional stacked memory cell structure. Multiple memory cell layers are vertically stacked on the substrate, enabling significant increase in integration degree while maintaining manufacturing feasibility through adapted fabrication processes
2Adaptability or versatility
If source voltage is applied to all local source lines simultaneously, then all memory blocks can operate, but source capacitance and current consumption increase
Solution Approach 1:
The patent divides the source voltage supply system into segmented regions controlled by individual source switches for each local source line. These switches enable selective activation of only the memory blocks requiring operation, thereby reducing overall current consumption while maintaining operational versatility
Solution Approach 2:
The patent implements dynamic control of source voltage distribution through source pass transistors that respond to block select signals. The system adaptively adjusts which local source lines receive voltage based on operational requirements, optimizing energy efficiency while preserving full operational capability when needed
3Device complexity
If multiple memory blocks share a common source line, then device complexity is reduced, but voltage drop increases and affects operational reliability
Solution Approach 1:
The patent segments the common source line into multiple independent local source lines, each serving specific memory blocks. Source switches at the intersection points enable selective connection, reducing voltage drop in active regions while maintaining a relatively simple overall architecture
Solution Approach 2:
The patent introduces source switches as intermediary components between the global source line and local source lines. These switches act as controlled connection points that minimize voltage drop by ensuring voltage is applied only to actively selected memory blocks, thereby improving operational reliability
Data Source
AI summary
A semiconductor device includes: one or more first source switches configured to control a connection between a global source line and a first local source line; one or more second source switches configured to control a connection between the global source line and a second local source line; a first memory block configured to operate using a first source voltage supplied through the first local source line; a second memory block configured to operate using a second source voltage supplied through the second local source line; a first source pass transistor configured to control the first source switch in response to a first block select signal; and a second source pass transistor configured to control the second source switch in response to a second block select signal.