Memory Device Source Line Voltage Control
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Solution Overview
Problem
Existing memory devices face challenges in efficiently programming memory cells without damaging the select transistors, particularly due to excessive voltage applied across the word line and source line.
Innovation Solution
The memory device incorporates a memory controller that applies distinct voltages to the bit line, word line, and source line during programming, ensuring that the voltage differences across the select transistor remain within safe limits, thereby preventing damage and allowing for reliable programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If high voltage is applied across the word line and source line during programming, then programming efficiency is improved, but the select transistor may be damaged due to excessive voltage
Solution Approach 1:
The voltage control is segmented into separate control mechanisms for different lines. The memory controller independently manages bit line, word line, and source line voltages, allowing high programming voltage to be applied to the bit line while maintaining safe voltage levels across the select transistor through coordinated control of the word line and source line.
Solution Approach 2:
The memory controller acts as an intermediary that mediates the voltage application process. It coordinates the timing and magnitude of voltages applied to the bit line, word line, and source line, ensuring that the select transistor is protected from excessive voltage while still enabling effective programming of the memory cell.
2Reliability
If separate voltage control is implemented for bit line, word line, and source line, then select transistor protection is improved, but device complexity increases
Solution Approach 1:
The memory controller is designed with multi-functionality to handle multiple voltage control tasks simultaneously. It manages bit line voltage, word line voltage, and source line voltage through integrated control circuits, reducing the need for separate dedicated control devices for each line and thereby managing complexity while achieving reliable protection.
Data Source
AI summary
Disclosed herein are related to a memory device including a set of memory cells and a memory controller. In one aspect, each of the set of memory cells includes a select transistor and a storage element connected in series between a corresponding bit line and a corresponding source line. In one aspect, the memory controller is configured to apply a first write voltage to a bit line coupled to a selected memory cell, apply a second write voltage to a word line coupled to a gate electrode of a select transistor of the selected memory cell during a first time period, and apply a third write voltage to a source line coupled to the selected memory cell. The second write voltage may be between the first write voltage and the third write voltage.