Semiconductor Memory Source Line Voltage Read Speed
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Solution Overview
Problem
Semiconductor memory devices face delays in read operations due to high wiring resistance in word lines, which affects the speed of continuous data reading.
Innovation Solution
The semiconductor memory device improves read operation speed by changing the voltage applied to the source line while maintaining a constant voltage on the word line, reducing delay by utilizing a lower resistance source line with many shunt wirings, and employing methods like ABL and bit-line shielding sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If word line voltage is changed during read operations to determine multiple threshold values, then memory cell threshold detection is achieved, but wiring resistance in word lines causes delays and reduces operation speed
Solution Approach 1:
The patent inverts the conventional approach by applying multiple different voltages to the source line instead of the word line during read operations. While conventional methods change word line voltage to detect different threshold values, this invention changes source line voltage levels (e.g., 0V, 2.5V, 4.0V) while maintaining constant word line voltage, thereby detecting multiple threshold values without suffering from word line resistance delays
Solution Approach 2:
The patent changes the voltage parameter applied to the source line across different read operations. By applying different voltage levels (0V, 2.5V, 4.0V) to the source line in successive operations, the system can determine multiple threshold values (first threshold, second threshold, third threshold) for multi-level cell data retrieval, achieving both measurement precision and operational speed
2Productivity
If continuous read operations are performed on multi-level cell memory, then data retrieval capability is enhanced, but wiring resistance accumulates delays across multiple operations
Solution Approach 1:
For continuous read operations on multi-level cells, the patent inverts the voltage application strategy by keeping word line voltage constant and varying source line voltage instead. This eliminates the cumulative delay problem that would occur with repeated word line voltage changes, enabling fast continuous retrieval of multiple threshold values (first, second, and third thresholds) from the same memory cell
Solution Approach 2:
The patent enables continuous read operations by maintaining constant word line voltage throughout the sequence of read operations while changing only the source line voltage. This continuous approach with constant word line voltage eliminates interruptions and delays between operations, allowing seamless retrieval of multiple threshold values from multi-level cell memory
Data Source
AI summary
A semiconductor memory device includes a memory cell, a word line electrically connected to a gate of the memory cell, and a source line electrically connected to a first end of the memory cell. During a read operation of the memory cell, a first voltage is applied to the source line in a first operation to determine whether or not a threshold voltage of the memory cell is above a first threshold value, a second voltage is applied to the source line in a second operation to determine whether or not the threshold voltage of the memory cell is above a second threshold value, and a third voltage is applied to the source line in a third operation to determine whether or not the threshold voltage of the memory cell is above a third threshold value.