3D Memory Source Select Line Structure for Simpler Etching
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Solution Overview
Problem
The manufacturing process of three-dimensional semiconductor memory devices is complex and requires innovative solutions to simplify the structure and fabrication methods, particularly in forming source select lines and gate stack structures to enhance operational reliability and efficiency.
Innovation Solution
The semiconductor memory device incorporates a cell stack structure with interlayer insulating layers and conductive patterns alternately disposed to surround channel structures, featuring source select lines with select gate layers and isolation structures to simplify the manufacturing process and improve operational reliability, including the use of slit formation to isolate select gate layers and reduce etching complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional manufacturing processes are used for three-dimensional semiconductor memory devices, then the device structure can be formed, but the manufacturing process becomes complex and requires multiple etching steps
Solution Approach 1:
The source select line is divided into multiple select gate layers (first, second, and third select gate layers) stacked in the vertical direction. Each layer serves a specific function in controlling the channel structure, allowing the manufacturing process to simplify etching operations while maintaining reliable transistor operation. The segmentation of the gate structure enables independent optimization of each layer's thickness and material properties.
Solution Approach 2:
The patent transitions from planar two-dimensional gate structures to three-dimensional vertically-stacked gate structures. The select gate lines are formed as multiple layers extending in the first direction (length direction) and stacked in the second direction (vertical direction), creating a three-dimensional configuration that surrounds the channel structure. This dimensional change allows for improved control of drain leakage current while simplifying the overall manufacturing process.
2Reliability
If the number of source select transistors is increased to improve operational reliability, then transistor control capability is enhanced, but the manufacturing complexity and device structure complexity increase
Solution Approach 1:
Multiple select gate layers (first, second, and third select gate layers) are merged into a single integrated source select line structure. These layers are formed simultaneously or in sequence as part of the same manufacturing process, eliminating the need for separate transistor fabrication steps. The merged structure provides enhanced control capability equivalent to multiple transistors while maintaining a unified manufacturing approach.
Solution Approach 2:
The multi-layer select gate structure serves multiple functions simultaneously: the first select gate layer provides primary selection control, the second select gate layer enhances control and reduces leakage, and the third select gate layer provides additional control capability. This universal structure replaces what would otherwise require multiple separate transistors, achieving multi-functionality within a single integrated component.
3Ease of manufacture
If conventional etching methods are used for select gate layers, then the etching process can be completed, but the etching complexity increases and manufacturing efficiency decreases
Solution Approach 1:
The patent optimizes the thickness parameters of each select gate layer to enable simplified etching. The first select gate layer has a thickness of 50-150 nm, the second select gate layer has a thickness of 30-80 nm, and the third select gate layer has a thickness of 30-80 nm. These parameter changes allow for selective etching with appropriate etch selectivities, reducing the number of etching steps required while maintaining manufacturing efficiency.
Solution Approach 2:
Interlayer insulating layers are introduced as intermediary structures between the select gate layers. These insulating layers provide etch stop functions and facilitate selective etching of the gate layers. The intermediary insulating layers enable simpler etching processes by creating distinct etching zones with different selectivities, thereby improving manufacturing efficiency without compromising the integrity of the gate structures.
Data Source
AI summary
There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a cell stack structure surrounding a first channel structure and a second channel structure; a first source select line overlapping with a first region of the cell stack structure and surrounding the first channel structure; and a second source select line overlapping with a second region of the cell stack structure and surrounding the second channel structure. Each of the first source select line and the second source select line includes a first select gate layer overlapping with the cell stack structure, a second select gate layer disposed between the first select gate layer and the cell stack structure, and a third select gate layer disposed between the first select gate layer and the second select gate layer.