Semiconductor Memory Device Source Line Voltage Control
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Solution Overview
Problem
In semiconductor memory devices with three-dimensionally disposed memory cells, voltage variations due to parasitic resistance in the source line can lead to malfunctions, as existing structures fail to maintain uniform electrical potential across the memory cells.
Innovation Solution
Incorporating a transistor under the source line, electrically connected via interconnect layers, to control and distribute voltage uniformly, thereby suppressing voltage drops and ensuring consistent potential distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a source line is used to electrically connect semiconductor pillars in three-dimensionally disposed memory cells, then the memory cells can be operated, but voltage variations increase due to parasitic resistance of the source line
Solution Approach 1:
A transistor is introduced as an intermediary component between the source line and the semiconductor pillars. The transistor includes a gate electrode that can be controlled to regulate the electrical connection, effectively mediating the voltage distribution and compensating for parasitic resistance effects in the source line.
Solution Approach 2:
The invention changes the electrical parameters (voltage and resistance characteristics) by introducing a controllable transistor element. By adjusting the gate voltage of the transistor, the effective resistance and voltage distribution in the source line connection can be dynamically controlled to maintain uniform potential across memory cells.
2Quantity of substance
If three-dimensionally disposed memory cells are implemented with stacked word lines and semiconductor pillars, then memory density is increased, but parasitic resistance in the source line causes voltage drops
Solution Approach 1:
The transistor serves as a mediating element that compensates for voltage drops caused by parasitic resistance. By controlling the transistor's conductive state through gate voltage, the system can maintain adequate voltage levels at the semiconductor pillars even when current flows through the resistive source line in high-density three-dimensional configurations.
3Device complexity
If the source line is positioned to connect semiconductor pillars directly, then the structure is simple, but uniform electrical potential cannot be maintained across memory cells
Solution Approach 1:
The transistor is positioned as an intermediary component between the source line and the semiconductor pillars, adding minimal structural complexity while significantly improving electrical potential uniformity. The transistor's gate electrode provides control over the electrical connection, ensuring stable potential distribution across all memory cells.
Solution Approach 2:
By introducing the transistor, the electrical parameters (conductivity, voltage distribution) can be dynamically adjusted to maintain uniform potential across memory cells, transforming the static and problematic direct source line connection into a controllable and stable electrical pathway.
Data Source
AI summary
A semiconductor memory device includes a plurality of word lines stacked in a first direction; a semiconductor pillar extending through the plurality of word lines in the first direction; a source line electrically connected to the semiconductor pillar; and a transistor arranged in the first direction with the plurality of word lines. The transistor includes a gate electrode, source and drain regions positioned on both sides of the gate electrode respectively. The source line is positioned between the transistor and the plurality of word lines, and is electrically connected to one of the source and drain regions.