Memory Structure Spacer Design for Coupling Ratio
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Solution Overview
Problem
Conventional memory structures face challenges with decreasing coupling ratios due to smaller memory cell sizes, requiring higher voltages for operation, leading to reduced efficiency and reliability, and suffer from parasitic transistor effects and electric leakage.
Innovation Solution
A memory structure design featuring a spacer with a higher top surface than the shallow trench isolation, preventing concave portion formation and electric leakage, while increasing the overlapping area between the floating gate and control gate, thus enhancing the coupling ratio.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the memory cell size is reduced to meet miniaturization requirements, then the physical size of the memory decreases, but the overlapping area of the floating gate and control gate decreases, resulting in lower coupling ratio
Solution Approach 1:
The patent introduces a spacer structure at the sidewall of the shallow trench isolation, creating a vertical dimension extension. This spacer causes the floating gate surface to form a curvature that extends beyond the original isolation boundary, effectively increasing the overlapping area in the vertical dimension while maintaining the same planar footprint, thus resolving the contradiction between miniaturization and coupling ratio maintenance
2Ease of manufacture
If wet etching process is used to remove pad oxide, then the pad oxide is removed from the substrate, but concave portions are formed on the sidewall of shallow trench isolation, causing electric leakage and manufacturing difficulties
Solution Approach 1:
The patent applies a spacer material to the sidewall of the shallow trench isolation before the wet etching process. This spacer acts as a protective layer that prevents the etching solution from attacking the isolation sidewall, thereby preventing concave portion formation and the associated electric leakage problems while still allowing complete pad oxide removal
3Volume of moving object
If higher voltage is applied on the control gate to compensate for low coupling ratio, then the memory can function with smaller cell size, but the efficiency and reliability of the memory decreases
Solution Approach 1:
By extending the floating gate overlap area into the vertical dimension through the spacer-induced curvature, the patent increases the coupling ratio without reducing the planar cell area. This maintains efficient operation at standard voltages while preserving miniaturization benefits, resolving the contradiction between cell size reduction and efficiency maintenance
Data Source
AI summary
A memory structure comprising a plurality of memory cells is described. Each memory cell comprises a substrate, a shallow trench isolation, a spacer, a tunnel oxide, and a floating gate. The shallow trench isolation in the substrate is used to define an active area. The spacer is at the sidewall of the shallow trench isolation and is higher than the shallow trench isolation. The tunnel oxide is on the active area. The floating gate is on the tunnel oxide.